International Business Machines Corporation

Globalfoundries Inc.

Globalfoundires Inc.

Kai D Feng

Hanyi Ding

Ping-Chuan Wang

Zhong-Xiang He

Zhijian Yang

Xuefeng Liu

Zhenrong Jin

Fen Chen

Wai-Kin Li

Elie Awad

Mariette Awad

Anthony K Stamper

Chengwen Pei

Louis Lu-Chen Hsu

David S Collins

Donald J Papae

Robert Mark Rassel

Yun Shi

Peter James Lindgren

John M Aitken

John S Austin

Anjali R Malladi

Shiu Chung Ho

Hailing Wang

Jong-ru Guo

Francis F Szenher

Trushil N Shah

Kafai Lai

Tom C Lee

Howard Hao Chen

Xiaojin Wei

Roger Aime Dufresne

Pinping Sun

J Edwin Hostetter

Hongfei Wu

Howard H Chi

Haitao O Dai

Richard J St-Pierre

Louis L Hsu

Robert J Gauthier, Jr

Zheng Xu

Alvin Jose Joseph

Robert Russell Robison

Michael Richard Ouellette

John Michael Cotte

Kenneth Joseph Goodnow

Duixian Liu

Dongbing Shao

Howard Smith Landis

David R Hanson

Dan Moy

Thomas J Fleischman

Emmanuel Yashchin

Seongwon Kim

Yang Liu

Essam Mina

Gregory John Mann

Serafino Bueti

Richard Andre Wachnik

Fernando Jose Guarin

Adam J Courchesne

Florian Braun

Nils Deneke Hoivik

Scott T Vento

Pui Ling Yee

Randall M Burnett, Ii

Edwin J Hostetter, Jr

Jon-ru Guo

Zhong-Xiang Ile

Geoffrey Woodhouse

Robert J Gautheir

An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

On-chip randomness generation

Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

Commonly-bodied field-effect transistors

A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

Physical unclonable interconnect function array

A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.

Structure and method for in-line defect non-contact tests

An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that generates sequential timing signals based on a period of the VCO from a frequency divided VCO signal, a frequency-to-voltage converter (FVC) that converts the frequency divided VCO signal into an output voltage, FVC, an internal reference voltage, and a voltage regulator that generates a control voltage, VCO, that is fed back to the VCO to lock a frequency of the VCO in the frequency-locked voltage regulated loop.

Frequency-locked voltage regulated loop

Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.

Air gap electrostatic discharge structure for high speed circuits

Method for fabricating a physical unclonable interconnect function array

Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

Embedded on-chip security

An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.

Frequency calibration with real-time resistor trimming

A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Precision trench capacitor

A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.

Ring oscillator testing with power sensing resistor

A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.

On-chip structure for security application

An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

Photoresist collapse method for forming a physical unclonable function

A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Semiconductor device including enhanced variability

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Hopewell Junction, NY, United States of America

Kai D Feng