Alpha Omega Semiconductor Inc.

Amazon Technologies, Inc.

Other

Maxim Integrated Products, Inc.

Intersil Americas Inc.

Rensselaer Polytechnic Institute

Crane Electronics, Inc.

Kai Chieh Liu

Ming Sun

Lei Shi

Jun Lu

Anup Bhalla

Xiaotian Zhang

François Hébert

Yueh-Se Ho

Yan Xun Xue

Leeshawn Luo

Hamza Yilmaz

Xiao Meng Zhang

Xi-Cheng Zhang

Jingzhou Xu

John Amato

Archiman Dutta

Yueh Se Ho

Xianshun Chen

Nikhil Anand Navali

Ruhi Sarikaya

Nikhil Vishwanath Kelkar

Xiaohu Liu

Tao Feng

Chenlei Guo

Kumar Nagarajan

James C Lee

Cuon Lam

Sovann Song

Karl Hillesland

Joe Pemberton

Xing Zhang

Khoa Nguyen

Mukul Agarwal

Kevin May

Jack Mousseau

Simon Fox

Lichao Wang

Dmitry Vladimir Zhiyanov

Bigyan Rajbhandari

Zhenyu Yao

Hung Tuan Pham

Zheng Du

Herman Chen

Satbir Madra

Zhao Liang

Argo Chang

Ryan Huang

Archi Dutta

Zahed Patel

Sriharsha Venkata Chintalapati

Techniques for performing centralized unsuperivised learning in a multi-domain system are described. A user may request labeled data for an ML task, where the request includes a prompt for obtaining relevant explicit user feedback. The system may use the prompt to collect explicit user feedback for relevant runtime user inputs. After a duration of time (in the user's request for labeled data) has elapsed, the system determines whether collected user feedback indicates processing of the user input was defective and, if so, determines a cause of the defective processing. The system then uses one or more label generators to generate labeled data using the collected user feedback, whether the processing was defective, and the determined defect cause.

Machine learning label generation

A hierarchical representation of an input data set comprising similarity scores for respective entity pairs is generated iteratively. In a particular iteration, clusters are obtained from a subset of the iteration's input entity pairs which satisfy a similarity criterion, and then spanning trees are generated for at least some of the clusters. An indication of at least a representative pair of one or more of the clusters is added to the hierarchical representation in the iteration. The hierarchical representation is used to respond to clustering requests.

Scalable hierarchical clustering

Entity record pairs are extracted from a selected cluster of entity records. Attribute value pairs are obtained from the entity record pairs. Labels are assigned to the attribute value pairs based at least in part on entity-level similarity scores of the entity records from which the attribute value pairs were obtained. A machine learning model is trained, using a data set which includes at least some attribute value pairs to which the labels are assigned, to generate attribute similarity scores for pairs of attribute values.

Artificial intelligence system using unsupervised transfer learning for intra-cluster analysis

Systems and methods are disclosed to implement a machine learned system to determine the comparative relationship between item package quantity (IPQ) information indicated in two item descriptions. In embodiments, the system employs a neural network that includes a token encoding layer, an attribute summarizing layer, and a comparison layer. The token encoding layer accepts an item description as a token sequence and encodes the tokens with token attributes that are relevant to IPQ extraction. The attribute summarizing layer uses a convolutional neural network to generate a set of fixed-size feature vectors for each encoded token sequence. All feature vectors for both item descriptions are then provided to the comparison layer to generate the IPQ comparison result. Advantageously, the disclosed neural network model can be trained to make accurate predictions about the IPQ relationship of the two item descriptions using a small set of token-level attributes as input signals.

Machine learned system for predicting item package quantity relationship between item descriptions

Systems and methods for displaying digital objects in multiple configurations based on a placement location within an Augmented Reality (AR) display. The systems are enabled to receive image data, identify multiple horizontal surfaces within the image data, and place a digital object model within the image data. The digital object model is placed in the AR display in a first configuration when placed with an anchor of the digital object model on a first horizontal surface and in a second configuration when placed with the anchor on a second horizontal surface.

Augmented reality object model configuration based on placement location

Systems and methods for providing peak current mode control (PCMC) for power converters using discrete analog components. A pair of complementary bipolar junction transistors may be used to set a maximum duty cycle for the power converter. PCMC may be achieved using a comparator that compares peak input current to an error feedback signal and terminates a pulse-width modulation (PWM) pulse when the peak input current exceeds the error feedback signal. A magnetic signal transformer may be used to establish a secondary side bias voltage supply, to return the error signal, and to drive an AC-coupled signal for a synchronous gate drive. A synchronous switch may be turned on when the main switch is turned off via an output winding of the flyback transformer and may be turned off by the trailing edge of a clock pulse from the magnetic signal transformer before the main switch is turned on.

Magnetic peak current mode control for radiation tolerant active driven synchronous power converters

Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts.

Embedded die redistribution layers for active device

A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Top exposed semiconductor chip package

A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Methods and configuration for manufacturing flip chip contact (FCC) power package

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Method for top-side cooled semiconductor package with stacked interconnection plates

The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Stacked dual chip package having leveling projections

A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Semiconductor package with connecting plate for internal connection

Semiconductor packaging method using connecting plate for internal connection

Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

Package leadframe for dual side assembly

A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Dual-leadframe multi-chip package

Growing community of inventors

Mountain View, CA, United States of America

Kai Chieh Liu