Intel Corporation

Kaan Oguz

Brian S Doyle

Mark L Doczy

Kevin O'Brien

Charles C Kuo

Christopher J Wiegand

Robert S Chau

Tanay Gosavi

Sasikanth Manipatruni

Ian A Young

David L Kencke

Satyarth Suri

Noriyuki Sato

Chia-Ching Lin

Elijah V Karpov

Roksana Golizadeh Mojarad

Benjamin Buford

Tahir Ghani

Uday Shah

Oleg Golonzka

Justin Brockman

Md Tofizur Rahman

Angeline Smith

Tofizur Rahman

Dmitri E Nikonov

Prashant Majhi

Gary Allen

Brian Maertz

John J Plombon

Abhishek A Sharma

Arnab Sen Gupta

Daniel Ouellette

Matthew V Metz

I-Cheng Tung

Ravi Pillarisetty

Van H Le

Niloy Mukherjee

Uygar E Avci

Urusa Alaan

Sou-Chi Chang

Juan G Alzate Vinasco

Clair C Webb

Hui Jae Yoo

Markus Kuhn

Tejaswi K Indukuri

Arijit Raychowdhury

Ryan E Arch

James Pellegren

Aleksandar Aleksov

Henning Braunisch

Kevin Lai Lin

Christopher J Jezewski

Yih Wang

Ashish Verma Penumatcha

Carl H Naylor

Thomas L Sounart

Nafees Kabir

Justin R Weber

Ayan Kar

Neelam Prabhu Gaunkar

Daniel B Bergstrom

Kevin P O'brien

Huiying Liu

Emily Walker

Sudarat Lee

Nicholas A Thomson

Michael Christenson

Punyashloka Debashis

Yong Ju Lee

Benjamin Orr

Yu-Jin Chen

Daniel G Oeullette

Atm G Sarwar

Kevin P OBrien

Ricky J Tseng

Rohan Patil

Ben Buford

Daniel Ouelette

Prashanth P Madras

Roksana Golizadeh Mojard

Daniel G Ouellette

Justin S Brockman

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

Differentially programmable magnetic tunnel junction device and system including same

Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

Capacitor with an electrically conductive layer coupled with a metal layer of the capacitor

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Compositional engineering of Schottky diode

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

ESD protection decoupled from diffusion

Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Low leakage thin film capacitors using titanium oxide dielectric with conducting noble metal oxide electrodes

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Capacitors with built-in electric fields

A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

Crystalline bottom electrode for perovskite capacitors and methods of fabrication

Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Monolithic memory stack

An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS, MoSe, WS, WSe, PtS, PtSe, WTe, MoTe, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Transition metal dichalcogenide based spin orbit torque memory device

An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

Nano-rod spin orbit coupling based magnetic random access memory with shape induced perpendicular magnetic anisotropy

An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO, (LaBi)FeO, LuFeO, PMN-PT, PZT, AlN, SmBiFeO, CrO, etc.) material and a transition metal dichalcogenide (TMD such as MoS, MoSe, WS, WSe, PtS, PtSe, WTe, MoTe, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

Transition metal dichalcogenide based magnetoelectric memory device

A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

Spin orbit memory devices with dual electrodes, and methods of fabrication

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer

A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.

Magnetic memory device with ruthenium diffusion barrier

A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

Antiferromagnet based spin orbit torque memory device

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Beaverton, OR, United States of America

Kaan Oguz