Xintec Corporation

Jyun-Liang Wu

Yen-Shih Ho

Chia-Sheng Lin

Po-Han Lee

Yi-Ming Chang

Hui-Hsien Wu

Hsiao-Lan Yeh

Shu-Ming Chang

Yu-Lung Huang

Chien-Min Lin

A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 &#x3bc;m to 750 &#x3bc;m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Chip package and manufacturing method thereof

A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

Growing community of inventors

Taichung, Taiwan

Jyun-Liang Wu