Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Vanguard International Semiconductor Corporation

National Yang Ming Chiao Tung University

Jyh-Chyurn Guo

Horng-Huei Tseng

Chenming Hu

Wai-Yi Lien

Da-Chi Lin

John Chern

W J Tsai

Ling-Yen Yeh

Chung-Long Chang

Denny Tang

Li-Shyue Lai

Kuo-Liang Yeh

Wen Chin Lin

Fu-Chia Shone

Wan-Yih Lien

Yen-Ying Lin

Wu-Der Wang

Ih-Chin Chen

A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.

Method for parameter extraction of a semiconductor device

A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area.

Parameter extraction method for semiconductor device

A method and system is disclosed for directing charged particles on predetermined areas on a target semiconductor substrate. After aligning a wafer mask with a semiconductor wafer, with the wafer mask having one or more mask patterns thereon, the charged particles are directed to pass through the mask patterns to land on one or more selected areas on the semiconductor wafer.

System and method for passing particles on selected areas on a wafer

A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Gate stack for high performance sub-micron CMOS devices

Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.

Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling

A tester for a semiconductor device is provided, which includes a bottom ground pad structure, an intermediate ground pad structure, and a top layer. The bottom ground pad structure is electrically connected to a substrate. The bottom ground pad structure includes a bottom signal shield plate. The intermediate ground pad structure is electrically connected to the bottom ground pad structure. The intermediate ground pad structure is located over the bottom ground pad structure. The top layer is located over the intermediate ground pad structure. The top layer includes a device under test (DUT), a ground probe pad, a signal probe pad, and leads. The DUT is electrically connected to the ground probe pad and the signal probe pad via the leads. The ground probe pad is electrically connected to the intermediate ground pad structure. The signal probe pad is located over the bottom signal shield plate.

Ground-signal-ground pad layout for device tester structure

A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer. Subsequent silicon oxide deposition and planarization procedures results in a first portion of the strained silicon layer overlying the silicon alloy layer while a second portion overlays a buried oxide region. A semiconductor device is then formed in the strained silicon layer, with specific elements of the semiconductor device located on a buried oxide region.

Non-floating body device with enhanced performance

Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.

Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses

A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH OH.

Pre-LDD wet clean recipe to gain channel length scaling margin beyond sub-0.1 &mgr;m

Method of fabricating a non-floating body device with enhanced performance

Within a method for fabricating a field effect transistor (FET) device there is provided a series of ion implant methods which provide the field effect transistor (FET) device with both: (1) a source region asymmetrically doped with respect to a drain region; and (2) an asymmetrically doped channel region. The field effect transistor (FET) device is fabricated with enhanced performance.

Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions

Within a method for fabricating a field effect transistor (FET) device within a microelectronic fabrication there is employed for forming a gate electrode from a blanket gate electrode material layer a self aligned two step pattering method. By employing the self aligned two step patterning method for forming the gate electrode, there may be formed within the field effect transistor (FET) device a source/drain region prior to forming interposed between the source/drain region and the gate electrode an additional ion implant structure while is formed while employing as a mask the gate electrode and a permanent spacer layer formed adjacent the gate electrode. By forming within the field effect transistor (FET) device the source/drain region prior to forming the additional ion implant structure, the additional ion implant structure is formed with enhanced structural stability, and thus the field effect transistor (FET) device is fabricated with enhanced performance.

Sacrificial spacer layer method for fabricating field effect transistor (FET) device

A method and methodology is provided for measuring ultra-low leakage current in DRAM devices. The invention provides a method and structures that are not limited to a trade-off between the number of contact points that are established to do the measurement and test accuracy, that can distinguish between diffusion junction leakage and leakage induced by contact regions and that can measure leakage current during on/off states of the word-line of a DRAM device.

Test structures for measuring DRAM cell node junction leakage current

A new flash memory cell structure and operational bias approach for allowing programming operations significantly faster than prior approaches, is based on the use of band-to-band tunneling induced hot electron injection in cells to be programmed and on the use of triple-well floating gate memory structures. The method comprises inducing band-to-band tunneling current from the semiconductor body to one of the source and drain near the channel, and applying a positive bias voltage to the control gate to induce hot electron injection into the floating gate. The other of the source and drain terminals is floated, that is disconnected so that current does not flow through that terminal. The band-to-band tunneling current is induced by applying a reference potential to one of the source and drain sufficient to establish conditions for the band-to-band tunneling current. For example, a reference potential of approximately 0 volts is applied to the drain, and negative bias of about &minus;4 volts to &minus;8 volts is applied to the semiconductor body, and a positive voltage is applied to the control gate which falls in a range of about &plus;6 volts to about &plus;10 volts.

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Hsinchu, Taiwan

Jyh-Chyurn Guo