Infineon Technologies Ag

Qimonda Ag

Jürgen Amon

Jürgen Faul

Thomas Schuster

Norbert Urbansky

Ralf Staub

Thomas Ruder

Ulrike Gruening

Matthias Goldbach

Johann Alsmeier

Frank Jakubowski

Dirk Offenberg

Albrecht Kieslich

Rudolf Strasser

Ralf Müller

A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure

A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Method for fabricating metallic bit-line contacts

A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Method for fabricating a semiconductor structure

Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.

The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS, GS, GS, GS) on a semiconductor substrate (), having the following steps: application of the gate stacks (GS, GS, GS, GS) to a gate dielectric () above the semiconductor substrate (); formation of a sidewall oxide () on sidewalls of the gate stacks (GS, GS, GS, GS); application and patterning of a mask () on the semiconductor structure; and implantation of a contact doping () in a self-aligned manner with respect to the sidewall oxide () of the gate stacks (GS, GS) in regions not covered by the mask ().

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Dresden, Germany

Jürgen Amon