Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Sumitomo Wiring Systems, Limited

Junya Fujita

Fumiki Aiso

Tomonari Shioda

Yoshiaki Fukuzumi

Takayuki Ito

Atsushi Fukumoto

Takashi Fukushima

Masahiro Kiyotoshi

Satoshi Nagashima

Hajime Nagano

Takeshi Sonehara

Takeshi Murata

Hisataka Meguro

Masataka Wakabayashi

Hideyuki Yamawaki

Toshiharu Nagumo

Saku Hashiura

Tatsuro Nishimoto

Keisuke Yagihashi

According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.

Semiconductor memory device including memory pillars and transistor and manufacturing method thereof

A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.

Semiconductor device and manufacturing method thereof

According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the buried layer. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and through the buried layer, and includes a sidewall portion positioned at a side of the buried layer. The silicon film is provided between the buried layer and the sidewall portion of the semiconductor body. The silicon film includes silicon as a major component and further includes at least one of germanium or carbon.

Semiconductor device

A compact protector is unlikely to be affected by electromagnetic noise and provides excellent workability when being assembled, despite having a configuration in which twisted electrical wires are not used. The protector includes first and second plate members that respectively have a plurality of parallel slits that have a depth that is approximately half a length of wiring areas in a widthwise direction of the wiring areas. First and second linear conductors are respectively supported by the first and second plate members such that the first and second linear conductors have an approximately wave-like shape that is bent in a lengthwise direction, a widthwise direction, and a thickness direction of the first and second plate members. The first and second plate members are laterally fitted to each other such that respective bottom parts of each pair of parallel slits that face each other are brought close to each other.

Protector

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer.

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.

Nonvolatile semiconductor memory device and manufacturing method thereof

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1&#xd7;10to 5&#xd7;10[atom/cm].

Nonvolatile semiconductor memory device

Growing community of inventors

Nagoya, Japan

Junya Fujita