Western Digital Technologies, Inc.

Sandisk Semiconductor (shanghai) Co. Ltd.

Sandisk Technologies Inc.

Morgan, Lewis & Bockius Llp

Junrong Yan

Chee Keong Chin

Weili Wang

Kim Lee Bock

Xiaofeng Di

Xin Lu

Zhonghua Qian

Xianlu Cui

Chong Un Tan

Ming Wu

Yang Lei

CheeKeong Chin

Chin-Tien Chiu

Li Ping Wang

Yu Wang

Shrikar Bhagath

Peng Lu

Cong Zhang

Gokul Kumar

Xin Hua Tian

Min Chao Zhao

Tao Shi

Qi Deng

Jian Bin Gu

Mingxia Wu

Pradeep Rai

Jianming Zhang

Yuyun Lou

Harjashan Singh

Xin Tian

C K Chin

Kailei Zhang

Hang Zhang

Jianbin Gu

Chaur Yang Ng

Chenlin Yang

Semiconductor dies formed on a wafer may be picked from the wafer with little or no stress, thus preventing cracking and damage to the semiconductor dies. A die attach film (DAF) layer is laminated onto an inactive surface of the wafer and the DAF layer is cut in the outline of the dies. The inactive surface of the wafer may then be supported on a vacuum chuck without using a dicing tape, and dies transferred from the wafer using a pick and place robot.

Semiconductor device with reduced stress die pick and place

A molding compound dispensing system identifies a semiconductor device strip having a substrate with a plurality of segments allocated for die stacks. The system obtains topological data of the identified semiconductor device strip for each of the segments, including data indicative of any semiconductor components in each respective segment. The system determines an amount of molding compound to be applied to each of the segments based on the topological data for each respective segment, and causes a molding compound dispenser to dispense the determined amounts of molding compound at each of the segments.

Mold compound dispensing system and method

A semiconductor device includes an integrated circuit die having bond pads and a bond wires. The bond wires are connected to respective ones of the bond pads by a ball bond. An area of contact between the ball bond and the bond pad has a predetermined shape that is non-circular and includes at least one axis of symmetry. A ratio of the ball bond length to the ball bond width may be equal to a ratio of the bond pad length to the bond pad width.

Wire bonding for semiconductor devices

A semiconductor device is vertically mounted on a medium such as a printed circuit board (PCB). The semiconductor device comprises a block of semiconductor dies, mounted in a vertical stack without offset. Once formed and encapsulated, side grooves may be formed in the device exposing electrical conductors of each die within the device. The electrical conductors exposed in the grooves mount to electrical contacts on the medium to electrically couple the semiconductor device to the medium.

Vertical semiconductor device with side grooves

A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

Sloped interconnector for stacked die package

A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.

Semiconductor device including vertical wire bonds

A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.

Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging

A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.

Semiconductor device with top die positioned to reduce die cracking

A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Semiconductor device including dual pad wire bond interconnection

A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.

Semiconductor device including corner recess

A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.

Semiconductor device including conductive bump interconnections

A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.

Semiconductor device including die bond pads at a die edge

A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

Spacer layer for embedding semiconductor die

Growing community of inventors

Shanghai, China

Junrong Yan