Sandisk Technologies Inc.

Junpei Kanazawa

Yoshitaka Otsu

Hisakazu Otoi

Takaaki Iwai

Masanori Terahara

Koichiro Nagata

Tatsuya Hinoue

Kengo Kajiwara

Shuji Minagawa

Atsushi Shimoda

Hironori Matsuoka

Muneyuki Imai

Raiden Matsuno

A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

Three-dimensional memory device including through-memory-level via structures and methods of making the same

A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

Three-dimensional memory device including multi-tier moat isolation structures and methods of making the same

A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

Three-dimensional memory device containing auxiliary support pillar structures and method of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.

Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same

A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.

Three-dimensional memory device containing a polygonal lattice of support pillar structures and contact via structures and methods of manufacturing the same

Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers with patterned stepped surfaces and an overlying retro-stepped dielectric material portion. The backside openings may be formed in rows with shape modifications in staircase regions to provide more lateral elongation in areas with lesser layers of the alternating stack. Non-circular horizontal cross-sectional shapes for the backside openings in the staircase regions allow formation of the backside opening with less shape distortion. Memory opening fill structures are formed in the memory openings, and the sacrificial material layers are replaced with electrically conductive layers using the backside openings as conduits for an etchant and for a deposition precursor material. The electrically conductive layers are isotropically recessed around each backside opening to form width-modulated cavities, which is filled with width-modulated insulating wall structures.

Three-dimensional memory device having double-width staircase regions and methods of manufacturing the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer include a second silicon oxide material having a greater density than the first silicon oxide material.

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Yokkaichi, Japan

Junpei Kanazawa