Fujitsu Corporation

Junji Sakurai

Hajime Kamioka

Kiyoshi Miyasaka

Tsutomu Ogawa

Haruhisa Mori

Seiichiro Kawamura

A method for producing a semiconductor device including the steps of forming an insulating layer on a substrate, the insulating layer having a plurality of concave portions, forming a non-single crystalline silicon layer on the surface of the insulating layer. The non-single crystalline silicon is patterned so that each concave portion is independently melted and the patterned non-single crystalline silicon layer flows into each of the concave portions to form a single crystalline region by irradiation with an energy ray; and, a semiconductor element is also formed in the single crystalline region.

Forming selective single crystal regions in insulated pockets formed on

A method of producing a semiconductor device includes the steps of preparing a base body, forming a non-single-crystalline semiconductor layer on the base body, and irradiating the non-single-crystalline semiconductor layer with an energy beam having a strip shaped irradiation region, in such a manner that either the base body or the energy beam is moved in a direction other than a scanning direction of the energy beam.

Method for producing a single-crystalline layer

A process for producing a monocrystalline layer on an insulator, particularly in a semiconductor wafer adapted for use to produce large-scale integrated circuits, comprising the steps of providing a nonmonocrystalline layer on an insulator and heating a region of the nonmonocrystalline layer by irradiating it from two heat sources while moving the heat sources relative to the nomonocrystalline layer, thereby locally melting and transforming the nonmonocrystalline layer to a monocrystalline layer.

Process for producing monocrystalline layer on insulator

Disclosed is a structure of a semiconductor integrated circuit device including circuit elements such as a bipolar transistor and I.sup.2 L. The structure comprises a buried layer formed by the ion implantation method using an insulating layer, having a window with tapered edges at the surface of semiconductor substrate, as a mask. A part of the buried layer appears at the surface of the semiconductor substrate, thus establishing the connection of electrodes. The circuit element is formed in the region bounded by the buried layer and the window.

Semiconductor bipolar integrated circuit device and method for

A horizontal furnace for processing semiconductor devices having a suspension cantilever which supports workpieces in the furnace tube to achieve particle or dust-free operation while still allowing the loading and unloading of workpieces to be heat-treated. The furnace tube consists of a heating chamber, a connecting chamber and a supporting chamber vertically connected to each other. The chambers correspond to an accommodating portion, a connecting portion and a supporting portion of the cantilever. The supporting chamber is kept at lower temperature than that of the heating chamber during heat processing to prevent deformation or creeping of the suspension cantilever.

Horizontal furnace with a suspension cantilever loading system

At present, the majority of semiconductor devices are two-dimensional large-scale integration (LSI) semiconductor devices in which the semiconductor elements are arranged in a semiconductor layer in a two-dimensional manner. An aim of the techniques of production of semiconductor devices is to achieve, in the future, a super high integration amounting to 16 M bits or more per chip. For attaining such a super high integration, a multilayer semiconductor device must be produced. A method for producing a three-dimensional LSI semiconductor device prevents wasteful formation of semiconductor layers and insulating films. The method includes the step of forming, in a first semiconductor layer, a monitoring device for evaluating the circuit function of the semiconductor elements in the first semiconductor layer and subsequently forming another semiconductor layer above the first semiconductor layer. A preferred embodiment also includes the steps of: forming the impurity regions of the semiconductor elements by ion implantation; activating the implanted impurity ions by energy beam irradiation; and forming the insulating material regions of the semiconductor elements by high-pressure oxidation, or by low-temperature sputtering.

Process for producing a three-dimensional semiconductor device

A highly integrated semiconductor memory device of a DMOS type, in which one half of the surface area in each memory cell is used as the drain region and another half is used as the gate electrode. The channel region and the source region are formed under the gate electrode so that, the size required by one memory cell is 4F.sup.2, where F represents the minimum width of a patterning line.

Highly integrated semiconductor memory device

A semiconductor memory system providing memory matrix area where many word lines and bit lines cross in the row and column directions. Memory cells are arranged at the intersections resulting in high integration density. A plurality of peripheral circuit blocks connected to adjacent plurality of word lines or bit lines. For example, the sense amplifiers and decoder circuits, etc., are sequentially arranged in files against the direction of the bit lines and word lines, respectively. Thereby, connections between the word lines or bit lines and the peripheral circuit blocks can be made without complicating the structure and using chip area ineffectively.

Semiconductor memory system

An equipment for implanting impurity material ions into a semiconductor wafer which supplies acceleration voltage and which continuously and automatically changes the acceleration voltage within a predetermined range for the purpose of producing impurity layers having a uniform concentration distribution in the direction of the depth of wafer. The equipment is effective in making fine patterns of integrated circuits. In one embodiment, the equipment changes the acceleration voltage continuously so that the frequency of the acceleration voltage is high enough to form a pillar shaped impurity layer at positions in a wafer while the ion beam is irradiated onto the positions respectively thereby to form an impurity layer having a uniform impurity distribution profile. In another embodiment of the invention, the equipment changes the acceleration voltage continuously but slow enough with respect to the scan frequency so that the ions are implanted to reach a certain depth in the first scan, another depth in the second scan and so on.

Ion implantation equipment

Shallow uniform impurity diffusion regions in a semiconductor substrate can be formed through the steps of forming an insulating film having a window on the semiconductor substrate, forming a semiconductor layer on the insulating film and semiconductor substrate exposed at the window, and diffusing a specified impurity from this semiconductor layer into the semiconductor substrate with the melt of semiconductor layer by a high energy beam such as a laser. Simultaneously, the melted semiconductor layer is recrystallized and is used as a contact electrode having a low resistance and extending from the impurity diffusion region. Diffusion of the impurity into the semiconductor layer, which is the impurity diffusion source, can be performed at the time of forming the semiconductor layer or after the formation of the semiconductor layer.

Method of manufacturing a semiconductor device

A method for forming a field isolation structure for a semiconductor device, in which a groove is formed in a semiconductor substrate, an insulating layer is formed on the substrate at least in the groove, a glass layer or a silicon layer is formed thereon, and thereafter a high energy beam such as a laser beam is irradiated onto the glass or silicon layer to selectively heat the same thereby to melt or fluidify the layer and let the same flow into the groove is disclosed. A smooth and flat surface is obtained through the above melting process, which also prevents electrical breaks in wiring layers formed thereon. The method is particularly suited to producing small field isolation structures thus improving the integration density of the device.

Method for manufacturing a field isolation structure for a semiconductor

In a process for producing a semiconductor device, buried regions are formed within the semiconductor substrate by introducing an impurity, an epitaxial layer is formed on the buried regions, and an energy beam is selectively irradiated on the surface of the epitaxial layer.

Process for producing a semiconductor device

Various improvements applicable to a method for production of a semiconductor device which is produced on a single crystalline semiconductor layer converted from a non-single crystalline semiconductor layer employing an energy ray irradiation process for conversion of non-single crystalline semiconductor to single crystalline semiconductor, including a process to make a scribing process more efficient realized by producing windows along scribe lines, a process for production of a planer type semiconductor device without damaging a converted single crystalline semiconductor layer realized by interposition of a field oxidation process and an energy ray irradiation process, a process enabling deep and uniform distribution of impurities without lateral diffusion in a semiconductor layer and a process for production of an embedded semiconductor resistor realized by employment of a mask made of a material not to allow radiated heat to pass therethrough, and a process for production of a mesa type semiconductor device not to allow discontinuity of wirings realized by employment of an energy ray irradiation process.

Method for production of semiconductor devices

An integrated semiconductor device having a plurality of IG FETs respectively formed an epitaxial semiconductor layer in plural apertures of a buried insulating film, and having regions for wiring extending under the buried insulating film within the semiconductor substrate. The wiring area has conductivity type opposite to the semiconductor substrate and functions to electrically connect between plural IG FETs. Thereby more complicated wirings can be realized. This region lying under the buried insulating film in the substrate can also function as the common well in the complementary type integrated semiconductor device and can eliminate the problem of defective operation which is likely to be caused in a complementary device having the buried insulating film.

Integrated semiconductor device having insulated gate field effect

A one transistor, one capacitance type dynamic MOS.RAM is provided with a buried storage capacitor and a planar transfer electrode. The MOS.RAM is, therefore, characterized by a small size of the memory cells and a simple production process. One process feature of the present invention is that a quick diffusion through polycrystalline silicon is employed for forming a vertical connection between the buried storage capacitor and the source or drain of the MOS transistor.

Growing community of inventors

Tokyo, Japan

Junji Sakurai