Kabushiki Kaisha Toshiba

Junichiro Noda

Kenichi Imamiya

Tamio Ikehashi

Daisuke Tohyama

A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.

Semiconductor device, method for testing the same and IC card

A semiconductor memory device includes a memory cell section having at least one memory cell using a cell transistor and a ferroelectric capacitor to store data. A sense amplifier is connected to the memory cell through a bit line. The device further includes an error checking and correction circuit which checks and corrects an error of data, which is read out of the memory cell by the sense amplifier, through the bit line.

Semiconductor memory device using ferroelectric capacitor, and semiconductor device with the same

A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.

Semiconductor memory device including page latch circuit

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to 'H,' a sense operation is performed. For reading data '0,' the SA node is rapidly increased to Vdd. For reading data &#x201c;1,&#x201d; the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Read circuit of nonvolatile semiconductor memory

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to &ldquo;H,&rdquo; a sense operation is performed. For reading data &ldquo;0,&rdquo; the SA node is rapidly increased to Vdd. For reading data &ldquo;1,&rdquo; the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Read circuit on nonvolatile semiconductor memory

An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to &ldquo;H,&rdquo; a sense operation is performed. For reading data &ldquo; ,&rdquo; the SA node is rapidly increased to Vdd. For reading data &ldquo; ,&rdquo; the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

A nonvolatile semiconductor memory device having a data reprogram mode comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form, a page buffer storing one page data to be programmed to memory cells which are selected in accordance with a page address signal, an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode which is a mode for erasing one page data stored in the memory cells which are selected in accordance with the page address signal and continuously programming the one page data stored in the page buffer to the memory cells which are selected.

Nonvolatile semiconductor memory device having a data reprogram mode

A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.

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Kanagawa-ken, Japan

Junichiro Noda