Nippon Telegraph and Telephone Public Corporation

Tohoku University

Other

Shin-etsu Handotai Co., Ltd.

Kokusai Electric Co., Ltd.

Hitachi Plant Engineering Construction Co., Ltd.

Junichi Murota

Takashi Matsuura

Masao Sakuraba

Yosuke Shimamune

Harushige Kurokawa

Tadahiro Ohmi

Takao Abe

Nobuo Mikoshiba

Fumihide Ikeda

Tetsushi Sakai

Nobuaki Ieda

Satoshi Nakayama

Shoichi Ono

Masafumi Tanimoto

Tsutomu Wada

Yoshimitsu Kitada

Takashi Watanabe

Terutaka Sahara

Masato Noda

Humihide Ikeda

Masuo Suzuki

Shigeru Takeda

Yutaka Hiratsuka

Tatuhiko Hurukado

Hideaki Takeuchi

Yoshio Fujisaki

Yutaka Sakakibara

A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 10 cm or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.

Semiconductor device having a metal-semiconductor junction with a reduced contact resistance

There is provided a novel bonded semiconductor wafer having a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more and manufactured by means of a bonding process, wherein at least one of the insulator layers is formed with ion implanted oxygen, and a novel manufacturing process for a bonded semiconductor wafer in which an ion implantation separation process is adopted. The novel bonded semiconductor wafer is manufactured by means of a bonding process and has a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more, wherein at least one of the insulator layers is formed with ion implanted oxygen.

Semiconductor wafer and method for producing the same

A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 10 cm or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.

A vapor deposition apparatus and method in which pulse waveform light is applied to a sample sealed in a reaction chamber. The sample is exposed to gaseous material while the pulse waveform light is applied creating one or plural atomic layers. Alternate layers of plural substances or alternate multiple layers of plural substances can be formed by alternating the introduction of gaseous materials with the application of pulse waveform light.

Vapor depositing method

A draft chamber is located within a clean room for sequentially immersing and processing carriers such as silicone wafers in a plurality of solution vessels provided in the draft chamber. In the draft chamber, a first air flow moves in a substantially horizontal direction from the front portion of the draft chamber toward the rear portion above the surfaces of solutions contained in chemical solution vessels which generate toxic gasses and a second air flow moves downward from the ceiling of the draft chamber. Thus, the toxic gasses generated from the chemical solution vessels are prevented from leaking into the clean room.

Draft chamber

A chemical vapor deposition apparatus has a reactor divided into a reaction space and a purging space by a susceptor for supporting a wafer and a loading chamber communicated through a gate with the reactor. Exhaust units are communicated with the reactor and loading chamber, respectively, so that the pressures in the reactor and loading chamber may be reduced. The susceptor has a plurality of recesses to aid placing or scooping the water. Through a transparent wall on the side of the purging space, the susceptor is heated by a lamp unit disposed outside the transparent wall. The loading chamber includes a wafer transport mechanism for charging a wafer into the reactor or discharging a processed wafer from the reactor. An unprocessed wafer is loaded to the loading chamber from a cassette and the processed wafer is unloaded to the cassette. One or a small number of wafers are processed at one time. A uniform film is deposited with a high reproducibility. The processing rate is high and the chemical vapor deposition apparatus is made compact in size.

Chemical vapor deposition apparatus

A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.

Irreversible semiconductor switching element and semiconductor memory

In an insulated gate type field effect transistor comprising spaced source and drain regions, an insulating film between the source and drain regions and a gate electrode mounted on the insulating film, an inverted frustum shaped polycrystalline semiconductor layer is formed on the insulating film and the gate electrode is mounted on the polycrystalline semiconductor layer.

Insulated gate type field effect transistors

Growing community of inventors

Sendai, Japan

Junichi Murota