Samsung Electronics Co., Ltd.

Seoul National University

Junghwan Moon

Woojin Kim

Hyungwoo Lee

Byunghoon Lee

Changyoung Jeong

Junghoon Bak

Maenghyo Cho

Muyoung Kim

Sungwoo Park

Byunggook Kim

Seowon Lee

Hyeongsun Hong

Youngyoon Woo

Joonmyung Choi

Minsik Jun

Nayoung Ji

An electronic device may include: a processor; a power amplifier; a power supply configured to supply power to the power amplifier; a crest factor reduction (CFR) module; and a digital predistortion (DPD) module, wherein the processor is configured to: transmit a first radio frequency (RF) signal, based on a first state of each of the CFR module, the DPD module, and the power supply, in a first transmission interval, the first RF signal being generated from a first baseband signal; identify voltage information of a second RF signal associated with a second transmission interval after the first transmission interval; change a state of each of the CFR module, the DPD module, and the power supply from the first state to a second state, based on the voltage information, in a first reception interval between the first transmission interval and the second transmission interval; and transmit the second RF signal generated from a second baseband signal based on the second state of each of the CFR module, the DPD module, and the power supply, in the second transmission interval.

Electronic device and method for amplifying transmission signal in time division duplex scheme

There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Lithography method using multi-scale simulation, semiconductor device manufacturing method and exposure equipment

A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Lithography method using multiscale simulation, and method of manufacturing semiconductor device and exposure equipment based on the lithography method

A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

Variable resistance memory device

Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern.

Magnetic memory devices for reducing electrical shorts between magnetic tunnel junction patterns

A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

Magnetic memory device

Growing community of inventors

Seoul, South Korea

Junghwan Moon