Samsung Electronics Co., Ltd.

Jungdal Choi

Changhyun Lee

Kwang Soo Seol

Youngwoo Park

Sunghoi Hur

Byeong-In Choe

Jaesung Sim

Sunil Shim

Jaehoon Jang

Jang-Gn Yun

Jintaek Park

Yoocheol Shin

Byungkyu Cho

Jaeduk Lee

Jaegoo Lee

Sangsu Kim

Kihwan Choi

Taeyong Kwon

Sung Gi Hur

Changseok Kang

Seunghyun Moon

Sung-il Chang

Jeonghyuk Choi

Kihyun Kim

Jae Ho Kim

Woonkyung Lee

Kwang-Soo Seol

Youngbae Kim

Masayuki Terai

Seungjae Jung

Dohyun Lee

Hyun-Sil Oh

Jung Moo Lee

Albert Fayrushin

Yong-lack Choi

Janggn Yun

Hyunjae Kim

Min Kyu Yang

Changyun Lee

Byeong-In Choi

Yongsik Yim

Hyunsu Ju

Eunmi Kim

Kwnag Soo Seol

YounSeon Kang

A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

Nonvolatile memory device and read method thereof

A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

Semiconductor devices and methods of fabricating the same

A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

Variable resistance memory device

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

Semiconductor device having fin-type field effect transistor and method of manufacturing the same

A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved.

Nonvolatile memory device and method of manufacturing the same

A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Three-dimensional semiconductor memory device

Resistive memory devices are provided having a gate stack including insulating layers and gates stacked on a substrate in a vertical direction, a channel penetrating the gate stack in the vertical direction to be electrically connected to the substrate, a gate insulating layer provided between the channel and the gates, and a variable resistance layer disposed along an extending direction of the channel. The gate stack may include an alcove formed by recessing the gate in a horizontal direction. The variable resistance layer may extend toward the alcove in the horizontal direction and be overlapped with at least one of the gates in the horizontal direction. Related methods are also provided.

Resistive random access memory devices having variable resistance layers and related methods

A read method of a vertical resistance memory device including resistance memory cells arranged in a three-dimensional array includes selecting a block from a plurality of blocks, applying a read voltage to a word line selected from word lines of the block, applying a sensing reference voltage to bit lines sharing the plurality of blocks, applying a string selection voltage to a string selection transistor through a string selection line selected from a plurality of string selection lines of the block, wherein the string selection line is connected to a gate of the string selection transistor; and determining a memory state of a memory cell selected from the plurality of resistance memory cells by the word line and the string selection line based on a current flowing through the memory cell, wherein the word line is connected through a corresponding horizontal electrode to the memory cell.

Vertical resistance memory device and a read method thereof

Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

Vertical nonvolatile memory devices and methods of operating same

A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

Nonvolatile memory device

Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

Nonvolatile memory devices, erasing methods thereof and memory systems including the same

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Hwaseong-si, South Korea

Jungdal Choi