Promos Technologies, Inc

Jung-Wu Chien

Chao-Hsi Chung

A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.

Manufacturing method of dynamic random access memory

A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

Gate structure and method for fabricating the same, and method for fabricating memory and CMOS transistor layout

A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

Method of forming contact plugs

A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate structure is disposed on the substrate and fills the trench. The doped region is disposed in the substrate at a first side of the gate structure. The deep trench capacitor is disposed in the deep trench of the substrate at a second side of the gate, and the second side is opposite to the first side. In addition, an upper electrode of the deep trench capacitor is adjacent to the bottom of the trench.

Dynamic random access memory (DRAM)

A memory charge storage node () is at least partially located in a trench (). The memory comprises a transistor including a source/drain region () present at a first side () but not a second side () of the trench. Before forming conductive material () providing at least a portion of the charge storage node, a blocking feature () is formed adjacent to the second side () to block the conductive material (). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask () comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion () at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side () rising above the top surface portion (T). The dielectric () on the trench sidewall has a portion () which is thicker on the second side than on the first side of the trench.

Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate

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Hsinchu, Taiwan

Jung-Wu Chien