Skhynix Inc.

Hynix Semiconductor Inc.

Sk Hynix Inc. Gyeonggi-do

Jung Ryul Ahn

Jum Soo Kim

Yun Kyoung Lee

Eun Seok Choi

Sang Hyun Oh

Sang Min Kim

Kang Sik Choi

Sang Yong Lee

Sung Mun Jung

Jung Seok Oh

Young Bok Lee

Se Hoon Kim

Yong Dae Park

In Geun Lim

Seung Bum Cha

Young Ki Shin

Ki Hong Lee

Min Kyu Lee

Se Jun Kim

Ji Hyun Seo

Byung Soo Park

Ki Seon Park

Hee Hyun Chang

Young Ok Hong

Hyun Seung Yoo

Byung Wook Bae

Won Sic Woo

Sung Yong Chung

Moon Sig Joo

Kyoung Hwan Park

Myung Shik Lee

Kyung Pil Hwang

Seung Hwan Baik

Yong Top Kim

Yong Mook Baek

Jae Young Park

A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.

Memory device and method of testing the memory device for failure

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Semiconductor device and manufacturing method of the same

A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Semiconductor device and manufacturing method of the semiconductor device

A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.

Manufacturing method of three-dimensional semiconductor memory device

A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.

Semiconductor memory device including three-dimensional array structure and memory system including the same

A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.

Semiconductor memory device including three-dimensional array structure

A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory string including a first cells portion and a second cells portion each including a multiple of memory cells, the second cells portion being disposed over the first cells portion, and a control logic configured to control a peripheral circuit such that each of at least two memory cells in a top of the first cells portion and each of at least two memory cells in a bottom of the second cells portion is programmed to have a smaller data bit than remaining memory cells in the first and second cells portions.

Semiconductor device with improved programming reliability

A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.

Semiconductor memory device

A semiconductor memory device, a memory system having the same, and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory cells electrically coupled between a source select transistor and a drain select transistor, a peripheral circuit configured to perform a program operation on the plurality of memory cells, and a control logic unit configured to control the operation of the peripheral circuit so that at least two memory cells of the plurality of memory cells adjacent to the source select transistor and at least two memory cells of the plurality of memory cells adjacent to the drain select transistor are programmed to have a relatively fewer number of data bits than that of remaining memory cells of the plurality of memory cells in the program operation.

Semiconductor memory device, memory system having the same, and method of operating the same

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Namyangju-si, South Korea

Jung Ryul Ahn