Samsung Electronics Co., Ltd.

Jung-hee Chung

Cha-young Yoo

Jae-hyoung Choi

Se-hoon Oh

Young-sun Kim

Sung-Tae Kim

Jeong-sik Choi

Se-Hoon Oh

Seok-Jun Won

Ki-chul Kim

Han-Mei Choi

Hyun-Suk Lee

Han-jin Lim

In-Sun Park

Jong-Cheol Lee

Yong-Kuk Jeong

Hyeon-Deok Lee

Yong-Suk Tak

Woo-Gwan Shim

Wan-don Kim

Nam-Kyu Kim

Jin-il Lee

Hyun-young Kim

Jin-Yong Kim

Yun-Jung Lee

Eun-ae Chung

Dae-Jin Kwon

Kwang-Hee Lee

Wan-Don Kim

Rak-Hwan Kim

Oh-seong Kwon

Woo-Sung Lee

Young-Joo Cho

Hyun-Seok Lim

Suk-jin Chung

Nam-Myun Cho

Hong-Bum Park

Hong-bum Park

Dong-kyun Park

Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Methods of forming integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same

Capacitors having composite dielectric layers containing crystallization inhibiting regions

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

Semiconductor devices having a contact plug and fabrication methods thereof

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode

Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.

Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same

Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors

Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

Methods of forming storage capacitors for semiconductor devices

A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.

Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs

Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capacitor to provide an ohmic contact therebetween. Forming a metal silicide layer may include exposing a surface of the conductive plug, depositing a metal layer of the bottom electrode on the exposed surface of the conductive plug and thermally processing the semiconductor device to react a part of the deposited metal layer and the conductive plug to form the metal silicide layer. Methods of forming a semiconductor device including a capacitor having a metal silicide layer connecting a bottom electrode of the capacitor and a conductive plug are also provided.

Methods of forming a semiconductor device including a metal silicide layer between a conductive plug and a bottom electrode of a capacitor

Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2&#x2013;1 ccm and oxygen at a flow rate of 20&#x2013;60 sccm, and depositing the ruthenium film at a temperature of 330&#x2013;430&#xb0; C. under a pressure of 0.5&#x2013;5 Torr using chemical vapor deposition (CVD).

Methods for forming ruthenium films with &#x3b2;-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same

In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.

Method of manufacturing capacitor by performing multi-stepped wet treatment on surface of electrode

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Seoul, South Korea

Jung-hee Chung