Taiwan Semiconductor Manufacturing Comp. Ltd.

Jung-Chien Cheng

Chih-Hao Wang

Kuo-Cheng Chiang

Shi Ning Ju

Kuan-Lun Cheng

Guan-Lin Chen

Shi-Ning Ju

Kuo-cheng Chiang

Yen-Ming Chen

Chia-Hao Chang

Jia-Chuan You

Kuan-lun Cheng

Bo-Rong Lin

A method of forming a semiconductor device includes etching trenches in a substrate to form semiconductor fins, filling a first one of the trenches with a dielectric fin, forming an insulation material in a second one of the trenches, performing a first recessing process to recess the insulation material and form a gap on a top of the dielectric fin, filling the gap with a dielectric cap, and forming a gate stack across the semiconductor fins and the dielectric fin.

Semiconductor device and formation method thereof

A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature including a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.

Semiconductor device structure including forksheet transistors and methods of forming the same

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Gap-insulated semiconductor device

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Semiconductor device structure

A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Nanosheet devices with hybrid structures and methods of fabricating the same

A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

Integrated circuit with backside trench for metal gate definition

A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method also includes forming a first metal gate stack wrapped around and extending across the first fin structure and the second fin structure. The method further includes forming a second metal gate stack wrapped around and extending across the first fin structure and the second fin structure. In addition, the method includes forming a protective structure extending into the first gate stack and forming a dielectric structure extending into the protective structure and the second metal gate stack. A portion of the protective structure is between the dielectric structure and the metal gate stack.

Structure and formation method of semiconductor device with isolation structure

An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source/drain region.

Transistor including downward extending silicide

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first channel structures and second channel structures formed over the substrate. The semiconductor structure also includes a dielectric fin structure formed between the first channel structures and the second channel structures. In addition, the dielectric fin structure includes a core portion and first connecting portions connected to the core portion. The semiconductor structure also includes a gate structure including a first portion. In addition, the first portion of the gate structure is formed around the first channel structures and covers the first connecting portions of the dielectric fin structure.

Semiconductor structure with dielectric fin feature

A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures. The first isolation feature is in physical contact with the first and second gate structures.

Semiconductor device with gate isolation features and fabrication method of the same

Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Hybrid semiconductor device

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

Nanostructure field-effect transistor device with dielectric layer for reducing substrate leakage or well isolation leakage and methods of forming

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to form a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.

Semiconductor device with gate isolation structure and method for forming the same

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.

Growing community of inventors

Hsinchu, Taiwan

Jung-Chien Cheng