Apple Inc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Nvidia Corporation

Advanced Semiconductor Engineering, Inc.

Jun Zhai

Kunzhong Hu

Chonghua Zhong

Sanjay Dabral

Vidhya Ramachandran

Mengzhi Pang

Shawn Searles

Kwan-Yu Lai

Jie-Hua Zhao

Tongbi T Jiang

Jared L Zerbe

Wei Chen

Emerson S Fang

Yizhang Yang

Chih-Ming Chung

Flynn P Carson

Se Young Yang

Joseph T DiBene, Ii

Raymundo M Camenforte

Caleb C Han

Timothy John Millet

Milind S Bhagavat

David A Secker

Jun Chung Hsu

Ralf M Schmitt

Zhitao Cao

Karthik Shanmugam

Wenjie Mao

Young Doo Jeon

John Bruno

Fei Wang

Thomas Hoffmann

Eric Tosaya

Chia-Ken Leong

Tom Ley

Ranjit Gannamani

Yifan Kao

Taegui Kim

Jung-Cheng Yeh

SivaChandra Jangam

Po-Hao Chang

Hsien-Che Lin

Ying-Chieh Ke

Jiongxin Lu

David A Pakula

Daniel William Jarvis

Dale R Setlak

Mohammad A Khan

Ian A Spraggs

Brad G Boozer

Richard C Blish

Raj N Master

Abraham Fong Yee

Michael Zhouying Su

Shakti Singh Chauhan

Gregory N Stephens

Dennis R Pyper

Rohan U Mandrekar

Meng Chi Lee

Amir Salehi

Lei Fu

James G Horiuchi

Derek J Walters

Patrick E O'Brien

Alex J Crumlin

David MacNeil

William Scott Lee

Joseph Minacapelli

Huabo Chen

Ashwin Balasubramanian

Leland W Lew

Michael Victor Yeh

David D Coons

Vu Thanh Vo

Jaime Bravo

Corey S Provencher

John Y Chen

Rajasekaran Swaminathan

Srinivasan Parthasarathy

Yun X Ma

Long Huang

Jinsu Kwon

Joe Greco

Menglu Li

Yi Xu

Mark G Walsh

Min-Shin Ou

Chun-Yang Lee

Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

Thermally enhanced chip-on-wafer or wafer-on-wafer bonding

Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

Microelectronic package RDL patterns to reduce stress in RDLs across components

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Interconnecting a plurality of dies having spare input/output circuit

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

High bandwidth die to die interconnect with package area reduction

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Wafer reconstitution and die-stitching

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

High density interconnection using fanout interposer chiplet

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Structure and method for sealing a silicon IC

Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

High density 3D interconnect configuration

Modules and methods of assembly are described. A module includes a lid mounted on a module substrate and covering a component. A stiffener structure may optionally be mounted between the lid and module substrate. A recess can be formed in any of an outer wall bottom surface of the lid, and top or bottom surface of the stiffener structure such that an adhesive layer at least partially fills the recess.

Recessed lid and ring designs and lid local peripheral reinforcement designs

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Selectable monolithic or external scalable die-to-die interconnection system methodology

Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

Flexible package architecture concept in fanout

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Multi-die fine grain integrated voltage regulation

Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

Fully interconnected heterogeneous multi-layer reconstructed silicon device

Interconnecting dies by stitch routing

Growing community of inventors

Cupertino, CA, United States of America

Jun Zhai