Southeast University

Realtek Semiconductor Inc.

Other

Google Inc.

Suzhou Sonavox Electronics Co., Ltd.

Suzhou Haider New Material Technology Co., Ltd.

Google Technology Holdings LLC

Yang, Jun

Crrc Nanjing Puzhen Haitai Brake Equipment Co., Ltd.

Jun Yang

Longxing Shi

Xinning Liu

Weiwei Shan

Chao Chen

Jian Liu

Peng Cao

Bo Liu

Na Bai

Shaojun Wei

Leibo Liu

Jianming Zhou

Shouyi Yin

Guoqiang Chai

Yuan Chen

Dengyong Ma

Hong Chang

Jia-Ning Lou

Shihua Li

Shih-hsiung Huang

Yang Zhang

Jie Li

Yen-Ting Wu

Jinjiang Yang

Jiafeng Zhu

Yue Feng

Cai Gong

Fei Pan

Yifeng Deng

Yingcheng Xia

Yuan Zhuang

Longning Qi

Heng-Chia Hsu

Qi Li

Wei Ge

Jingjing Guo

Hao Sun

Chen Hu

Wei-Xiong He

Lixuan Zhu

Zhi-Xian Gao

Lian-Sheng Zhang

Zhifeng Wu

Ziyu Li

Chen Dai

Xiao-Jeng Zhu

Xiangyu Wang

Haolin Gu

Xiao-Feng Zhu

Yu Gong

Jianliang Mao

Xiangyang Liu

Jinfeng Ma

Bingqian Xu

Mengxiao Li

Wentao Dai

Yanyin Chen

Pengcheng Yang

Fuping Han

Pengfei Qu

Yongsheng Mu

He Zhu

Jinlun Fu

Jianhua Li

Yefeng Cai

Wenhua Zhao

Yinhu Liu

Shen Xing

Yunzhe Du

Zhengzhuan Yang

Kang Hu

Sa Zhao

Joji Takase

The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under 'negative margin', the system can further lower voltage, compress the timing slack, and obtain higher power gain.

Ultra low-power negative margin timing monitoring method for neural network circuit

A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.

Method for predicting fluctuation of circuit path delay on basis of machine learning

A core material for a shock insulation support, comprising, in parts by weight: steel shot of 150-300 parts, zirconia particles of 50-150 parts and rubber particles of 50-100 parts. Further provided are a shock insulation support comprising the core material, and a preparation method for the shock insulation support. The core material for a shock insulation support, and the shock insulation support dissipates earthquake energy by means of a dry friction energy dissipation mechanism, having high damping and excellent shock insulation performance.

Core material for shock insulation support, shock insulation support having friction core and preparation method therefor

A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.

Successive approximation register analog to digital converter device and signal conversion method

A driving current includes a first and second push-pull circuits which each includes a first and second output terminals and a first to fourth transistors. The first to fourth transistors are series connected. At least one of control terminals of the first and second transistors of the first push-pull circuit and at least one of control terminals of the third and fourth transistors of the second push-pull circuit receive a positive input signal. At least one of control terminals of the third and fourth transistors of the first push-pull circuit and at least one of control terminals of the first and second transistors of the second push-pull circuit receive a negative input signal. The first output terminals output a pair of first signals. The second output terminals output a pair of second signals.

Driving circuit and signal converting circuit

The present invention provides a generalized proportional integral observer-based method for compensating for visual-measurement time lag of an electro-optical tracking system. For visual-measurement time lag present in an electro-optical tracking system, an improved generalized proportional integral observer-based feedback control method is used to mitigate the impact of the measurement time lag on the system and suppress kinematic uncertainty of the system. The core of the method lies in that an observer is used to estimate a state, uncertainty, and a difference of the system at a previous moment, a state and uncertainty of the system at a current moment are then calculated by using these estimated values and a state-space model of the system, and a control input of the system is finally acquired according to the estimated values of the state and uncertainty of the system at the current moment. The method mitigates the adverse impact of visual-measurement time lag on the system and enhances the uncertainty suppression and the tracking precision of the system.

Method for compensating for visual-measurement time lag of electro-optical tracking system

The present invention discloses a voltage conversion circuit having self-adaptive mechanism. A control branch includes a first resistor coupled between a second power supply and a control terminal, and a switch circuit that is coupled between the control terminal and a ground terminal and receives an input voltage from an input terminal to generate a control voltage at the control terminal. A voltage-withstanding P-type transistor circuit of an output branch is coupled between the second power supply and the output terminal that generates an output voltage and is controlled by the control voltage. A voltage-withstanding N-type transistor circuit of the output branch is coupled between the output terminal and the ground terminal and is controlled by an inverted input voltage. When the input voltage is at a first power domain high/low state, the output voltage is at a second power domain high/low state.

Voltage conversion circuit having self-adaptive mechanism

The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

Charge pump device

A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

Clock control device and clock control method

A high energy efficiency switched-capacitor power converter includes the transmission gates T-T, the capacitors C-C, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence, the on-chip capacitor C, the capacitor Cand the load capacitor CL are charged in series. In the state of timing sequence, the capacitor Cand the capacitor Care connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C, the capacitor C, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.

High energy efficiency switched-capacitor power converter

An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

Ultra-low-power mode control circuit for power converter

A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM, a second PMOS transistor PM, a third PMOS transistor PM, a fourth PMOS transistor PM, a fifth PMOS transistor PM, a first bias voltage VB, a second bias voltage VB, a third bias voltage VB, a first N-channel metal oxide semiconductor (NMOS) transistor NM, and a second NMOS transistor NM. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

Wide voltage trans-impedance amplifier

An amplifier device includes an alternate current (AC) coupling circuit, an amplifier circuit, and a first bias circuit. The amplifier circuit is configured to amplify an input signal to generate an output signal, in which the amplifier circuit includes a first input terminal, and the first input terminal receives the input signal via the AC coupling circuit. The first bias circuit is configured to apply a first bias voltage to the first input terminal according to one of the output signal and a first voltage, such that the amplifier circuit amplifies the input signal to output the output signal.

Amplifier device

A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PMto PMOS transistor PM. The two resistors include resistor Rand resistor R. The two capacitors include capacitor Cand capacitor C. The three NMOS transistors include NMOS transistor NM, NMOS transistor NMand NMOS transistor NM. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM-PMform a feedback circuit. The feedback circuit clamps the current flowing through PMto be proportional to PMto obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PMaccording to the change of load current to output different currents according to the load demand.

Low-temperature drift ultra-low-power linear regulator

Growing community of inventors

Jiangsu, China

Jun Yang