Taiwan Semiconductor Manufacturing Comp. Ltd.

Jun Xiu Liu

Kai-Lin Chuang

Chung-Pin Chou

Yan-Cheng Chen

Chi-Hsuen Chang

Chung-I Chen

Tzu-Chiang Sung

Tsung-Chi Chen

Pei-Jung Chang

Chun-Wei Huang

Chia-Wei Liu

Sheng-Wen Huang

Rann Shyan Yeh

Chih Po Huang

Sheng-Ching Kao

Rann-Shyan Yeh

Shiue-Ming Guo

Sheng He Huang

Hsuan-Chia Kao

Tsung-Yi Huang

Chun-Chih Lin

Chien-Mao Chen

Han-Wen Liao

Hsin Kuan

Cuker Huang

Zhi-Cheng Chen

Jieh-Ting Cheng

Jui Kuo Lai

An apparatus for inspecting a semiconductor substrate includes a rotatable base configured to support a substrate, and a nozzle arm includes a nozzle and a light monitoring device. The light monitoring device includes a laser transmitter and an array of light sensors arranged in the nozzle arm and facing the substrate. The light monitoring device is configured to transmit a laser pulse towards the substrate, wherein the laser pulse impinges on the substrate, receive a reflected laser pulse from the substrate, calculate whether one or more light sensors received the laser pulse, and calculate a distance between the light monitoring device and the substrate using the turnaround time for determining a process quality on the substrate.

Apparatus and methods for determining fluid dynamics of liquid film on wafer surface

A method of manufacturing a semiconductor device includes: receiving a workpiece on which the semiconductor device is manufactured; causing a nozzle to dispense a fluid toward a surface of the workpiece external to the nozzle, wherein the nozzle includes a first channel and a second channel that allow the fluid to flow through; emitting light, by a light source, from within the nozzle toward the surface while the nozzle is dispensing the fluid; receiving light reflected from the surface by a light sensor, the light source and the light sensor being disposed within the nozzle and opposite to each other, and the emitted light and the reflected light adapted to be contained within the fluid; and examining a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of each of the first channel and the second channel.

Nozzle having real time inspection functions

In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.

System and method for high speed inspection of semiconductor substrates

Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.

Semiconductor processing tool and methods of operation

A method of monitoring a fluid includes: applying the fluid from within a nozzle to a surface of a wafer outside of the nozzle; emitting light, by a light source, from the nozzle to the surface; receiving light reflected from the surface by a light sensor and causing the reflected light to propagate into the nozzle; and determining whether a variation of the fluid occurs according to the reflected light.

Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Methods of enhancing surface topography on a substrate for inspection

A nozzle for emitting a fluid comprises a channel, a light source and a light sensor. The channel is configured to flow the fluid. The light source is configured to emit light towards a surface on which the fluid is applied and the light sensor is configured to receive reflected light from the surface.

A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

Semiconductor structure for isolating integrated circuits of various operating voltages

A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common Nburied layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common Pburied layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

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A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage

A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

Self-aligned method for defining a semiconductor gate oxide in high voltage device area

Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

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Taichung, Taiwan

Jun Xiu Liu