Taiwan Semiconductor Manufacturing Comp. Ltd.

Jun Wu

Ying-Lang Wang

Chyi-Tsong Ni

Shih-Chi Lin

Wen-Long Lee

Szu-An Wu

Chi-Wen Liu

Shiu-Ko JangJian

Yi-Lung Cheng

Jowei Dun

Guang-Cheng Wang

Shiu-Ko Jangjian

Michael Chang

Ying-Lung Wang

Hway-Chi Lin

Yu Ku Lin

Ming Jer Lee

Dong-Xuan Lu

Yi-An Jian

A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200&#xb0; C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Low temperature method for minimizing copper hillock defects

A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

Method of smoothening dielectric layer

A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Methods of spin-on wafer cleaning

A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same

A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (&ldquo;fresh&rdquo;) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

Rework method for wafers that trigger WCVD backside alarm

Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

Three-dimensional type inductor for mixed mode radio frequency device

Growing community of inventors

Taoyuan County, Taiwan

Jun Wu