Samsung Electronics Co., Ltd.

Jun-Soo Bae

Jang-Eun Lee

Hyun-Jo Kim

Se-Chung Oh

Young-Ki Ha

Hideki Horii

Kwang-Jin Lee

Bong-jin Kuh

Yong-Ho Ha

Kyung-tae Nam

In-gyu Baek

Jeong-Hee Park

Woo-Yeong Cho

Beak-Hyung Cho

Ji-Hye Yi

Jong-Chan Shin

Mi-Lim Park

Kyu-Man Hwang

Ju-Chul Park

Seung-Woo Lee

Hyeong-Geun An

Dong-ho Ahn

Young-Soo Lim

Shi-Jung Kim

Du-Eung Kim

Byung-Gil Choi

Hye-Jin Kim

Ki-sung Kim

Won-Jun Lee

Dong-Ho Ahn

Suk-Hun Choi

Doo-Hwan Park

Sung-Un Kwon

Joon-Sang Park

Jong-Soo Seo

Kyung-Tae Nam

Kwang-Ho Park

Jong-bong Park

Young-Kug Moon

Eun-Hee Cho

Myung-jin Kang

Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

Magnetic random access memory devices and methods of manufacturing the same

A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

Phase change memory devices and methods of manufacturing the same

Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Methods of forming phase-changeable memory devices including an adiabatic layer

In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.

Multi-level phase change memory device, program method thereof, and method and system including the same

A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by InSbTeor, alternatively, with substitutions of silicon and/or tin for indium, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer.

Non-volatile memory device including phase-change material

A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.

Method fabricating semiconductor device using multiple polishing processes

A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Variable resistance memory device and system thereof

A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Phase change memory devices and systems, and related programming methods

Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

Nonvolatile memory device, storage system having the same, and method of driving the nonvolatile memory device

A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Magnetic memory device

A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Multi-layer phase-changeable memory devices

Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

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Hwaseong-si, South Korea

Jun-Soo Bae