Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Zentel Japan Corporation

Jun Setogawa

Tsukasa Ooishi

Takashi Kubo

Takeshi Hamamoto

Kenichi Yasuda

Masaru Haraguchi

Bunsho Kuramori

Akihiro Hirota

Hironori Iga

Minoru Senda

Mineo Noguchi

Masahiro Ishihara

Takuya Ishida

Mitsuru Yoneyama

A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Semiconductor memory device for preventing occurrence of row hammer issue

The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.

Semiconductor device

A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.

Semiconductor memory device invalidating improper control command

A detection circuit in a semiconductor memory device includes a first latch circuit and a second latch circuit. The first latch circuit latches a data strobe signal at a rise of a clock signal after a write latency passes. The second latch circuit receives an output signal of the first latch circuit at a rise of a clock signal to output a detection signal. Circuits in the semiconductor memory device are controlled by a detection signal. With such an operation applied, the semiconductor memory device grasps a correct phase difference between a data strobe signal and a clock signal, thereby enabling a normal operation.

Semiconductor memory device with detection circuit

The output of a ring oscillator that receives an internal power supply potential as an operating power supply potential to conduct an oscillation operation is counted by a counter that receives an external power supply potential as an operating power supply potential, and reset is canceled. The circuit that operates with an internal power supply potential can be reliably reset even when the rise of the internal power supply potential is delayed. By adjusting the number of stages of the inverter of a ring oscillator and the number of bits of the counter, the power-on reset time can be adjusted while suppressing increase of the area. An appropriate power-on reset signal can be generated to prevent erroneous operation even in the case where the rise of the internal power supply potential lags behind the rise of the external power supply potential.

Semiconductor device capable of reliable power-on reset

The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.

Semiconductor memory device having function of supplying stable power supply voltage

In a semiconductor memory device, its clock buffer includes a first comparator having a pair of P channel MOS transistors whose gates receive a clock signal and a complementary clock signal, respectively, and a second comparator having a pair of N channel MOS transistors whose gates receive the clock signal and the complementary clock signal, respectively. An internal signal is generated in response to an output signal of the comparator having a shorter response time which starts correspondingly to the cross point where the clock signal and the complementary clock signal cross each other. Even if the level of the cross point is scattered, a scatter in the response time of the internal signal which starts correspondingly to the cross point becomes small.

Input buffer of a semiconductor device that gives only a small scattering in delay time

An internal clock signal generating circuit includes a phase comparing circuit which is made active in accordance with a control signal SEN which becomes intermittently active in a power down mode from an operation permission signal generating circuit, receives an external clock signal and an output from a delay circuit, and compares phases of the signal and the output with each other, an address generating circuit for receiving a phase comparison result and generating a delay amount control signal for controlling a delay amount, and an address decoder for receiving an output of the delay circuit and generating a decode signal for controlling the delay amount.

Semiconductor storage device with suppressed power consumption and reduced recovery time from suspend mode

When a first data bus line and a second data bus line as a pair are used as a complementary bus, a complementary data signal ZDATA is provided to the second data bus line, and an output buffer circuit that becomes unnecessary is rendered inactive. On the other hand, when the first and second data bus lines are used as two single data buses, a differential amplifier transmits two data signals without amplification to the first and second data bus lines. A data signal DATA is provided to the second data bus line. The output buffer circuit is activated, and a data signal ZDATA is output from an output node.

Semiconductor device allowing switchable use of internal data buses

When the frequency of an external clock signal is higher than a prescribed frequency in an SDRAM, an output signal from a clock frequency detection circuit is at an L level, a transfer control signal is fixed to an H level, and first and second data buses are coupled together. Thus, a malfunction when the transfer control signal attains an H level in a pulse manner while read data is not output to the first data bus can be prevented. Accordingly, an SDRAM having a larger operating frequency range can be obtained.

Synchronous type semiconductor memory device

A reference voltage generating circuit and a standby down-converting circuit or a tuning circuit are located in the periphery of the region where a semiconductor device is formed on a semiconductor chip, and a region including an active down-converting circuit which operates during an active cycle or a drive circuit is located adjacent to a circuit actually consuming a current. According to the semiconductor device, increase in area can be suppressed compared to the structure in which both a standby down-converting circuit or drive circuit and the tuning circuit and an active down-converting circuit are located in the vicinity of each current consuming circuit, thereby achieving efficient arrangement of the internal power supply circuitry. As a result, a semiconductor device having efficiently arranged internal power supply circuitry is provided.

Growing community of inventors

Hyogo, Japan

Jun Setogawa