Denso Corporation

Denso Corpora Tion

Toyota Jidosha Kabushiki Kaisha

Nippondenso Co., Ltd.

Jun Sakakibara

Hitoshi Yamaguchi

Shoji Mizuno

Akiyoshi Asai

Hirotaka Saikaku

Tetsuo Fujii

Yoshiyuki Hattori

Tsuyoshi Yamamoto

Yuichi Takeuchi

Yasushi Urakami

Toshiyuki Morishita

Shoichi Yamauchi

Toshio Sakakibara

Masakiyo Sumitomo

Naohiro Suzuki

Makoto Kuwahara

Takumi Shibata

Megumi Suzuki

Rie Taguchi

Takeshi Enya

Nozomu Akagi

Seiji Fujino

Masaki Matsui

Yuma Kagata

Nobuhiro Tsuji

Yoshitaka Noda

Takanari Sasaya

Kunihiro Onoda

Hisayoshi Ohshima

A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

Silicon carbide semiconductor device and method for manufacturing same

A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.

Method for manufacturing silicon carbide semiconductor device

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Semiconductor device having switching element and free wheel diode and method for controlling the same

A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short.

Semiconductor device including schottky barrier diode and method of manufacturing the same

A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

Semiconductor device having super junction MOS transistor and method for manufacturing the same

A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.

Semiconductor device having super junction

A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.

Semiconductor device having p-n column portion

A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.

Semiconductor device and method for manufacturing the same

A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein the epitaxial semiconductor layer is disposed in the first trench. The first trench includes an inner wall as an interface between the semiconductor substrate and the epitaxial semiconductor layer so that the interface provides a PN junction. The first trench has an aspect ratio equal to or larger than 1.

A semiconductor device includes a base P region, a source Nregion, and a drain Nregion formed in a surface layer portion on a principal surface in an Nsilicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain Nregion in a region including the drain Nregion and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain Nregion from the source Nregion as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.

Horizontal MOS transistor

A first trench is formed in a surface of an n-type semiconductor substrate that forms a source region. A p-type base region, an n-type drift region, and an n-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.

Semiconductor device having high breakdown voltage without increased on resistance

A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si&lcub;100&rcub; surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si&lcub;100&rcub; surfaces.

Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench

In a semiconductor device, a p-type base region is provided in an n -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n -type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n -type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n -type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Method of manufacturing semiconductor device having trench filled up with gate electrode

A first trench is formed in a surface of an n -type semiconductor substrate that forms a source region. A p-type base region, an n -type drift region, and an n -type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n -type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.

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Anjo, Japan

Jun Sakakibara