Skhynix Inc.

Jun Phyo Lee

Hyung Sik Won

Seung Han Oak

Sang Ah Hyun

Woo Sik Jung

Bong Hwa Jeong

Yong Ho Seo

A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.

Test systems configured to perform test mode operations for multiple memory devices

A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Semiconductor device with memory banks and sense amplifier arrays

Growing community of inventors

Gyeonggi-do, South Korea

Jun Phyo Lee