Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Jun Ohtani

Tsukasa Ooishi

Akira Yamazaki

Hiroshi Kato

Katsumi Dosaka

Tomoya Kawagoe

Hideto Hidaka

Yasuhiko Taito

Naoto Okumura

Mitsuhiro Hamada

Masatoshi Ishikawa

Takashi Higuchi

At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data

Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair

A potential of &#x2212;3V is applied to a control gate electrode, a potential of 5V is applied to a pair of impurity regions and a potential of 3V is applied to a semiconductor substrate in a non-volatile semiconductor memory device. Accordingly, electrons existing on one impurity region side in a silicon nitride film move toward that impurity region, and electrons existing on the other impurity region side move toward that impurity region. Furthermore, electrons existing in that part (middle part) of the silicon nitride film which is positioned immediately above a region approximately at the middle point between one impurity region and the other impurity region move toward the semiconductor substrate. Therefore, MPE (Miss Placed Electron) is no longer caused in the non-volatile semiconductor memory device.

Method of erasing information in non-volatile semiconductor memory device

A semiconductor memory device according to the present invention includes: a data line switching circuit including a plurality of switches which selectively connect one of a plurality of normal data lines and spare data lines included in a memory cell array to one of a plurality of global data lines for transmitting input/output data to the memory cell array; and a switching control circuit including a shift decoder having decode circuits for decoding a defective address stored in a program circuit as many as the switches.

Semiconductor memory device for improvement of defective data line relief rate

In a non-volatile semiconductor memory device, three word line voltage circuits generating different voltages are provided. A voltage selecting circuit pre-selecting one voltage from the three different voltages is provided. In an ONO film in which lower silicon oxide film is formed thinner than upper silicon oxide film, word line voltage generating circuit is pre-selected, and in a write operation a voltage of 7V lower than the normal voltage of 9V is applied. In ONO film in which upper silicon oxide film is formed thinner than lower silicon oxide film, word line voltage generating circuit is pre-selected, and in a write operation a voltage of 11V higher than the normal voltage of 9V is applied. Thus, the non-volatile semiconductor memory device capable of retaining charges as information stably is attained.

Non-volatile semiconductor memory device having a memory cell which stably retains information

At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.

Non-volatile semiconductor memory device capable of rapid operation

A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

Semiconductor memory device

A thin film magnetic memory device includes a plurality of program cells each storing program data constituting information on a bit unit basis, each program cell having a magnetic storing part having first and second electric resistors corresponding to two magnetization directions. The thin film magnetic memory device further includes: a driver circuit for irreversibly fixing a resistance value of the magnetic storing part in the program cell to a third electric resistor; and a sense driver circuit capable of sensing whether the magnetic storing part in the program cell has the first or second electric resistance and capable of sensing whether the magnetic storing part in the program cell has any one of the first or second resistances, or the third electric resistance.

Thin film magnetic memory device capable of stably writing/reading data and method of fabricating the same

In each word line driver, an output node is precharged to a power supply voltage prior to a row select operation and disconnected from the power supply voltage in the row select operation. Further, each first node is connected to a corresponding second node selectively driven to a ground voltage according to a row address through a control switch that is turned on in the row select operation. In each shift switch, output nodes corresponding to word lines other than a defective word line and spare word lines are connected to a second node of a corresponding word line or a word line adjacent thereto through a plurality of transistor switches selectively turned on in accordance with shift control, respectively.

Semiconductor memory device with word line shift configuration

When a non-volatile memory cell which can store two bits per one memory cell and pass current bidirectionally is used, a bias power source potential is provided also to a bit line BL adjacent to two bit lines (BL and BL ) passing a sense current BL and BL Switch units are provided corresponding to each bit line for selectively connect to any one of a ground power source line, read power source line or bias power source line. The current flowing from a sense amplifier circuit to the adjacent bit line BL via adjacent memory cell can be reduced, and thus the current in the sense amplifier circuit is stabilized quickly. Accordingly, a non-volatile semiconductor memory device allows high-speed data reading operation.

Non-volatile semiconductor memory device capable of high-speed data reading

A memory cell in a MRAM includes four N channel MOS transistors responsive to a write permit signal attaining an H level to connect program lines of first and second tunneling magneto-resistance elements between first and second storage nodes and a line of ground potential to write signals in the first and second storage nodes to the first and second tunneling magneto-resistance elements. The writing of signals to first and second tunneling magneto-resistance elements can be performed more rapidly than the conventional case where signals in the first and second storage nodes are read out, and then written into the tunneling magneto-resistance elements via a write circuit and a write bit line pair.

Semiconductor memory device with latch circuit and two magneto-resistance elements

Each of program units which is arranged to be adjacent to a memory array, stores redundant information of 1 bit necessary for replacement and repair. Prior to normal data read operation, the redundant information read from the program units is latched in a row select circuit. The row select circuit selectively activates one of word lines corresponding to the normal memory cells and a spare word line in accordance with whether the defective row addresses indicated by the redundant information are matched to an inputted row addresses, respectively.

Thin film magnetic memory device having redundancy repair function

A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.

Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell

In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

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Hyogo, Japan

Jun Ohtani