Alpha & Omega Semiconductor Corporation

Alpha and Omega Semiconductor (cayman) Ltd.

Alpha and Omega Semiconductor International LP

Radiant Networks Plc

Other

Lsi Corporation

Jun Lu

Yan Xun Xue

Hamza Yilmaz

Yueh-Se Ho

Ming-Chen Lu

Anup Bhalla

Zhiqiang Niu

Xiaotian Zhang

Lei Shi

Kai Chieh Liu

Ping Huang

Liang Zhao

Yan Huo

François Hébert

Hua Pan

Yuping Gong

Hongtao Gao

Bum-Seok Suh

Long-Ching Wang

Tao Feng

Allen Chang

Madhur Bobde

Kai Chen

Peter L Wilson

Wonjin Cho

Xiaoguang Zeng

Zhi Qiang Niu

Shuhua Zhou

Yan Yun Xue

Man Sheng Hu

Guo Feng Lian

Daniel Ng

Xiaobin Wang

Ming Sun

Yi Qiang Su

John Amato

Tushar Ramanlal Shah

Manouchehr S Rafie

Lei Duan

Aihua Lu

Jianxin Ye

De Mei Gong

Fei Wang

Junho Lee

Hossein Dehghan

Hongyong Xue

Son Tran

Yuwei Zhang

Yu Gong

Syang-Myau Hwang

Xiaorong Ge

Hong Fu

Demei Gong

Jong-Mu Lee

Dengwei Fu

Mary Jane R Alin

Xiaoming Sui

Kevin Hwang

Shue-Lee Chang

Lin Lv

Guobing Shen

Xi Huang

Kai Lu

Zhen Du

GuoFeng Lian

Kal Liu

Alex Niu

Ping Hoang

Jacky Gong

Xiaolian Zhang

Le Shi

Wanki Hong

Kenny Man Sheng Hu

Francois Hébert

A power module includes a lead frame, a substrate mounted on the lead frame, a first anchor pad, a second anchor pad, a plurality of die pads, and a plurality of transistor dies. The lead frame includes a first lead frame anchored bar attached to the first anchor pad, and a second lead frame anchored bar attached to the second anchor pad. The power module may include a single control IC or two or more control ICs. For the case including a single control IC, the singe control IC controls a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. For the case including two control ICs, a low voltage IC controls a first transistor, a second transistor, and a third transistor and the high voltage IC controls a fourth transistor, a fifth transistor, and a sixth transistor.

Semiconductor power module package having lead frame anchored bars

A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 μm to 35 μm. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.

Chip scale package (CSP) semiconductor device having thin substrate

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

Semiconductor package having thin substrate and method of making the same

A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.

DMOS FET chip scale package and method of making the same

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.

Semiconductor package having high mechanical strength

An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RJC) compared to a conventional IPM.

Molded intelligent power module for motors

A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Power semiconductor device with small contact footprint and the preparation method

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Molded intelligent power module and method of making the same

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

Molded intelligent power module

A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures

The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes

A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures.

Preparation method of a thin power device

A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced.

Power semiconductor package device having locking mechanism, and preparation method thereof

Growing community of inventors

San Jose, CA, United States of America

Jun Lu