Yangtze Memory Technologies Co., Ltd.

Wuhan Telecommunication Devices Company

Hubei Boshilong Technology Co., Ltd.

Jun Liu

Weihua Cheng

Li Hong Xiao

Zongliang Huo

Yu Ting Zhou

Zhiliang Xia

Jun Chen

Zhenyu Lu

Yushi Hu

Jifeng Zhu

Qian Tao

Lei Xue

Zi Qun Hua

Zhao Hui Tang

Zhaosong Li

Sizhe Li

Yi Bu Li

Lu Ming Fan

Yi Hua Liu

Zhi Yang

Qiangmin Wei

Dasheng Jiang

Zhiyi Cheng

Shouqi Liu

Yu Li

Yingfei Wang

Shiyan Wu

Weihua Chen

A semiconductor device in a multi-chip package (MCP) includes a controller, at least one non-volatile memory die including an array of non-volatile memory cells and connected to the controller through wire bonding, and at least one volatile memory die including an array of volatile memory cells and connected to the controller through wire bonding. The controller is configured to control operations of the at least one non-volatile memory die and the at least one volatile memory die.

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

A semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts and a first dielectric layer isolating the first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including second bonding contacts and a second dielectric layer isolating the second bonding contacts. The first bonding layer is bonded to the second bonding layer. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure.

Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same

In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

Bonded semiconductor devices having processor and static random-access memory and methods for forming the same

A method for forming a three-dimensional (3D) memory device includes the following operations. First, in a first semiconductor structure, logic process-compatible devices and first bonding contacts are formed conductively connected to the logic process-compatible devices. In a second semiconductor structure, an array of NAND memory cells and second bonding contacts are formed conductively connected to the array of NAND memory cells. A first surface of an interposer structure is bonded to the second semiconductor structure. First interposer contacts disposed at the first surface of the interposer structure are conductively connected to the second bonding contacts. A second surface of the interposer structure is bonded to the first semiconductor structure. Second interposer contacts disposed at the second surface of the interposer structure are conductively connected to the first bonding contacts. The interposer structure is attached to the first semiconductor structure and the second semiconductor structure.

Methods for forming semiconductor devices bonded by interposer structure

Aspects of the disclosure provide a method of tilting characterization. The method includes measuring a first tilting shift of structures based on a first disposition of the structures. The structures are formed in a vertical direction on a horizontal plane of a product. A second tilting shift of the structures is measured based on a second disposition of the structures. The second disposition is a horizontal flip of the first disposition. A corrected tilting shift is determined based on the first tilting shift and the second tilting shift.

Method for tilting characterization by microscopy

LED phototherapy device

Electronic cupping device

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one first semiconductor structure includes a programmable logic device, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one second semiconductor structure includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one die includes the bonded first and second semiconductor structures.

Bonded semiconductor devices having programmable logic device and dynamic random-access memory and methods for forming the same

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Multiple-stack three-dimensional memory device and fabrication method thereof

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.

Integration of three-dimensional NAND memory devices with multiple functional chips

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Stacked connections in 3D memory and methods of making the same

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.

Semiconductor devices having adjoined via structures formed by bonding and methods for forming the same

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

Growing community of inventors

Wuhan, China

Jun Liu