Kabushiki Kaisha Toshiba

Jun-ichi Okano

Shigeo Yawata

Yoshikazu Usuki

Shun-ichi Hiraki

Shigeru Moriyama

Kiyohito Matsumoto

According to this invention, there is provided to a method of manufacturing semiconductor devices including the steps of ion-implanting at least one impurity selected from As, P, Sb, Si, B, Ga, and Al in a wafer prior to a predetermined manufactural process of semiconductor devices in the semiconductor wafer grown by the Czochralski technique, and thereafter annealing the wafer at a temperature of at least 900.degree. C. Nonuniformity of an impurity concentration of the wafer can be improved. The difference in characteristics among the semiconductor devices manufactured in the wafer is decreased, a product yield can be increased, and the quality of the semiconductor devices can be improved.

Method of rendering the impurity concentration of a semiconductor wafer

A method for manufacturing cascaded junction type field effect transistors comprises the steps of forming an epitaxial layer of a first conductivity type used as a channel region on a semiconductor substrate of a second conductivity type and performing selective oxidation to form a thick oxide film on part of the epitaxial layer. Then, the thick oxide film is removed to provide a part of the surface which is a level lower than the main surface of the epitaxial layer. Next, an impurity of the first conductivity type is doped into the low and high surface areas of the epitaxial layer from the surface thereof to form source and drain regions separated at a preset distance. After this, an impurity of the second conductivity type is doped into the low and high level surface areas of the epitaxial layer between the source and drain regions to simultaneously form first and second junction gates which are separated at a present distance. Then, the semiconductor substrate is connected to the second junction gate and source region to connect two junction FETs in cascade fashion.

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Hyogo, Japan

Jun-ichi Okano