Apple Inc.

Jun Chung Hsu

Flynn P Carson

Meng Chi Lee

Shakti Singh Chauhan

Tha-An Lin

Jun Zhai

Yifan Kao

Taegui Kim

Yikang Deng

Kwan-Yu Lai

Jie-Hua Zhao

Chih-Ming Chung

Young Doo Jeon

Shatki S Chauhan

An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

Asymmetric Stackup Structure for SoC package substrates

Asymmetric stackup structure for SoC package substrates

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

Semiconductor packaging substrate fine pitch metal bump and reinforcement structures

Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Substrate-less integrated components

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

Vertical interconnects for self shielded system in package (SiP) modules

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Self shielded system in package (SiP) modules

Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a 'known good' substrate on a support substrate.

Carrier ultra thin substrate

A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.

Methodology to achieve zero warpage for IC package

A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

Growing community of inventors

Cupertino, CA, United States of America

Jun Chung Hsu