Fairchild Semiconductor Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Taiwan Semiconductor Manufacturing Comp. Ltd.

Nano Silicon Pte. Ltd.

Seagate Technology Incorporated

Institute of Microelectronics

Jun Cai

Ruey-Hsin Liu

Keng Foo Lo

Jim G Holt

David Hu

Hsueh-Liang Chou

Chun-Wai Ng

Chi-Chih Chen

Michael Harley-Stead

Brian Thomas Edgar

Jun Song

Jeetandra Kella

Hsiao-Chin Tuan

Chih-Wen Yao

Alex Kalnitsky

Narayanan Balasubramanian

Pang Dow Foo

Guang Ping Hua

ChuanPeng Ong

Alvin Sugerman

Micheal Harley-Stead

Steven Park

Mark A Gaertner

Ting Cheong Ang

Shyue Fong Quek

Feng Shen

Harry Tiotantra

Puay Ing Ong

WeiQing Zhou

Kai C Chen

Wajid Ali

JianZhong Zhang

Thaik Thaik Aung

Yonqzang Zhang

AndiSumaryo Sutiawan

Xin Li

A method includes receiving at a storage device a command from a host. When learning is active on the storage device, an initial parameter value of a plurality of parameter values is used for performing a first action of a plurality of actions for the command. The first action is performed using the initial parameter value of the plurality of parameter values for the command The first parameter value is incremented to a next parameter value of the plurality of parameter values for the command for use in reperforming the first action.

Onboard machine learning for storage device

Systems and methods are disclosed for resource allocation for multi-actuator systems. In some examples, a data storage device can include two or more independently moveable voice coil motor (VCM) actuators where the resources of the system to operate the VCM actuators are divided. The disclosure here describes methods to allocate or re-allocate the divided resources, such as unused resources, to a VCM actuator that has a need for more resources. The methods and systems herein can also be applied to other actuator systems.

Resource allocation for multi-actuator storage device

An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method provides for determining that a sequence of incoming write commands are associated with an LBA range mapped to a source band and writing data of the incoming write commands to physical blocks of a destination band assigned to the LBA range of the source band such that the data of the incoming write commands is written according to a sequential order of data receipt and in a forward write direction to sequentially fill physically-consecutive blocks in the destination band.

Fragmented data storage bands

An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Lateral DMOS device with dummy gate

A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.

Semiconductor device with localized carrier lifetime reduction and fabrication method thereof

Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.

Seeding mechanism for error detection codes

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

Localized carrier lifetime reduction

A device includes one or more data storage media having a main storage area, and includes a non-volatile cache memory and a controller. The controller stores a plurality of data packets into a plurality of physical locations in the main storage area. Each of the data packets is associated with a different logical block address (LBA), and each of the physical locations is associated with a different physical location address (PLA). The controller generates mapping information that links the different LBAs to the different PLAs. Upon detecting a soft error when reading a data packet stored in a physical location, the controller relocates the data packet associated with the soft error to a physical location of the non-volatile cache memory. The controller also marks the physical location as a suspect location. The controller updates the mapping information to reflect the relocation of the data packet associated with the soft error.

Data reallocation upon detection of errors

An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Stepped-source LDMOS architecture

A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

High-voltage diodes formed in advanced power integrated circuit devices

A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device is in an on state, current tends to flow deeper into the drift region to the offset gate, rather than near the device surface. The drift region preferably includes at least first and second stacked JFETs. The first and second stacked JFETs include first, second and third layers of a first conductivity type, a fourth layer intermediate the first and second layers including alternating pillars of the first conductivity type and of a second conductivity type extending between the source and drain regions; and a fifth layer intermediate the second and third layers, including alternating pillars of the first and second conductivity types extending between the source and drain regions.

High voltage LDMOS

Growing community of inventors

Scarborough, ME, United States of America

Jun Cai