International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Globalfoundaries Inc.

Julien Frougier

Ruilong Xie

Kangguo Cheng

Chanro Park

Nicolas J Loubet

Veeraraghavan S Basker

Daniel Chanemougame

Heng Wu

Min Gyu Sung

Andrew Mark Greene

Steven J Bentley

Ali Razavieh

Dimitri Houssameddine

Juntao Li

Chen Zhang

Alexander Reznicek

Junli Wang

Edward J Nowak

Jingyun Zhang

Bipul C Paul

Huimei Zhou

Bruce Bennett Doris

Dechao Guo

Balasubramanian Pranatharthiharan

Pietro Montanini

Puneet Harischandra Suvarna

Hui Zang

Kisik Choi

Andreas Knorr

Steven R Soss

Nigel Graeme Cave

Lawrence Alfred Clevenger

Carl John Radens

Oleg Gluschenkov

Lars W Liebmann

Ruqiang Bao

Su Chen Fan

Ravikumar Ramachandran

Yi Qi

Miaomiao Wang

Brent A Anderson

Hiroaki Niimi

Eric R Miller

Christopher Joseph Waskiewicz

Sagarika Mukesh

Tenko Yamashita

Shogo Mochizuki

Takeshi Nogami

Wenyu Xu

Min-Hwa Chi

Roy Rongqing Yu

Siva P Adusumilli

Albert Manhee Chu

Anthony I Chou

Randy W Mann

Frank Wilhelm Mont

Robin Hsin Kuo Chao

Baofu Zhu

Arkadiusz Malinowski

Keith Donegan

Chih-Chao Yang

Anthony K Stamper

Takashi Ando

Effendi Leobandung

Guy M Cohen

Mukta G Farooq

Michael Rizzolo

Judson Robert Holt

Zhenxing Bi

Soon-Cheon Seo

Reinaldo Ariel Vega

Ekmini Anuja De Silva

Haiting Wang

Yann Mignot

Guillaume Bouche

Xuefeng Liu

Xusheng Kevin Wu

Chun-Chen Yeh

Indira P Seshadri

Cheng Chi

Lan Yu

Bartlomiej Jan Pawlak

Zhenyu Hu

Srikanth Balaji Samavedam

William James Taylor, Jr

Rishikesh Krishnan

Albert M Young

Andre P Labonte

Jay William Strane

Tao Li

Daniel J Jaeger

George Robert Mulfinger

Hsien-Ching Lo

Ryan W Sporer

Ardasheir Rahman

Jia Zeng

Adra Carr

Christopher Michael Prindle

Prasad Bhosale

Hemant M Dixit

An exemplary semiconductor apparatus includes a substrate that includes a first semiconductor. The substrate includes a main body and first and second island portions protruding upward from the main body. The apparatus also includes a bottom dielectric isolation layer that covers the substrate; a PFET with a plurality of gate-all-around (GAA) vertical channel fins above the first island portion and the bottom dielectric isolation layer; and an NFET with a plurality of gate-all-around (GAA) horizontal nanosheet layers above the second island portion and the bottom dielectric isolation layer.

Optimizing stress in a hybrid vertical-PFET and horizontal-NFET nanosheet structure

A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

Direct backside self-aligned contact

A semiconductor structure including stacked transistor structures each including a top device stacked directly above a bottom device, and a placeholder dielectric and a backside gate contact within a dielectric capping layer beneath the stacked transistor structures, where the placeholder dielectric is directly below a first bottom source drain region, and the backside gate contact is directly below a second bottom source drain region.

Stacked transistors having self aligned backside contact with backside replacement metal gate

One or more systems, devices, and/or methods of fabrication provided herein relate to nanosheet transistors with support dielectric pillars. According to one embodiment, a transistor device can comprise an active transistor fin and a support dielectric pillar located adjacent to the active transistor fin, wherein the support dielectric pillar stabilizes the active transistor fin.

Support dielectric fin to prevent gate flop-over in nanosheet transistors

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and a dielectric nanosheet as a top layer of the nanosheet stack is provided above a semiconductor substrate. A dummy gate with a gate cap and spacers on the sidewalls straddle over the nanosheet stack. End portions of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer material layer is formed. A source/drain region is formed on the sidewalls of each semiconductor channel material nanosheet. The dummy gate and gate cap are removed. Each sacrificial semiconductor material nanosheet is removed. A functional gate structure is formed that wraps around each suspended semiconductor channel material nanosheet. A self-aligned source/drain contact region is formed. A gate contact region is formed in a trench in the semiconductor substrate.

Self-aligned contact (SAC) in nanosheet transistors

Interconnect structures including parallel metal lines and cut regions in selected ones of the parallel metal lines are fabricated without damage, even at a very small metal pitch. A dielectric fill in the cut regions has a smaller width than the width of the metal lines. Metal line width can be increased by selective metal deposition on sidewalls of the metal lines subsequent to forming the cut regions.

Interconnect structure including patterned metal lines

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

Enhanced linerless vias

A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.

Gate-all-around field-effect-transistor with wrap-around-channel inner spacer

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

Liner-less via contact

A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Semiconductor device having hybrid middle of line contacts

A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Heterogeneous gate all around dielectric thickness

Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

Integration of nanosheets with bottom dielectric isolation and ideal diode

A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Phase-change memory device with conductive cladding

A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.

MRAM-based chip identification with free random programming

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Semiconductor backside contact structure with increased contact area

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Albany, NY, United States of America

Julien Frougier