International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Globalfoundaries Inc.

Julien Frougier

Ruilong Xie

Kangguo Cheng

Chanro Park

Nicolas J Loubet

Daniel Chanemougame

Veeraraghavan S Basker

Heng Wu

Steven J Bentley

Ali Razavieh

Andrew Mark Greene

Min Gyu Sung

Dimitri Houssameddine

Chen Zhang

Alexander Reznicek

Juntao Li

Junli Wang

Edward J Nowak

Jingyun Zhang

Bipul C Paul

Huimei Zhou

Bruce Bennett Doris

Dechao Guo

Balasubramanian Pranatharthiharan

Pietro Montanini

Puneet Harischandra Suvarna

Hui Zang

Andreas Knorr

Steven R Soss

Nigel Graeme Cave

Carl John Radens

Lars W Liebmann

Ruqiang Bao

Ravikumar Ramachandran

Kisik Choi

Yi Qi

Miaomiao Wang

Lawrence Alfred Clevenger

Oleg Gluschenkov

Hiroaki Niimi

Su Chen Fan

Eric R Miller

Christopher Joseph Waskiewicz

Sagarika Mukesh

Brent A Anderson

Tenko Yamashita

Shogo Mochizuki

Takeshi Nogami

Wenyu Xu

Min-Hwa Chi

Roy Rongqing Yu

Siva P Adusumilli

Randy W Mann

Frank Wilhelm Mont

Robin Hsin Kuo Chao

Baofu Zhu

Arkadiusz Malinowski

Sung Dae Suk

Chih-Chao Yang

Anthony K Stamper

Takashi Ando

Effendi Leobandung

Mukta G Farooq

Michael Rizzolo

Judson Robert Holt

Zhenxing Bi

Soon-Cheon Seo

Ekmini Anuja De Silva

Haiting Wang

Yann Mignot

Guillaume Bouche

Xuefeng Liu

Xusheng Kevin Wu

Albert Manhee Chu

Anthony I Chou

Chun-Chen Yeh

Indira P Seshadri

Cheng Chi

Lan Yu

Bartlomiej Jan Pawlak

Srikanth Balaji Samavedam

Zhenyu Hu

William James Taylor, Jr

Rishikesh Krishnan

Andre P Labonte

Jay William Strane

Albert M Young

Tao Li

Daniel J Jaeger

George Robert Mulfinger

Hsien-Ching Lo

Ardasheir Rahman

Ryan W Sporer

Adra Carr

Jia Zeng

Christopher Michael Prindle

Hemant M Dixit

Prasad Bhosale

Eric Miller

Karthik Yogendra

A method including forming a plurality of nanosheets on a substrate and forming a plurality of sacrificial layers on the substrate, wherein the plurality of nanosheets and the plurality of sacrificial layers are arranged as alternating layers. Forming and patterning a first hardmask located on top of one of the sacrificial layers and forming a second hardmask around the first hardmask. Patterning the plurality of nanosheets and the plurality of sacrificial layers. Forming and patterning a dummy gate located on top of first hard mask. Removing the plurality of sacrificial layers. Forming a plurality of nanowires, where the plurality of nanowires is formed by the removal of the plurality of sacrificial layers, where the removal of the plurality of sacrificial layers thins sections of each of the plurality of nanowires forming the plurality of nanowires.

Nanowire source/drain formation for nanosheet device

A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.

Buried power rail with robust connection to a wrap around contact

Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Strain generation and anchoring in gate-all-around field effect transistors

A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Semiconductor structure with wrapped-around backside contact

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

Method and structure of forming sidewall contact for stacked FET

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.

Semiconductor structure having stacked power rails

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

Full wrap around backside contact

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

Resistive switching memory cell

A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. Wherein the widths Wand Ware different from each other and the lengths Land Lare different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Gate-all-around nanosheet-FET with variable channel geometries for performance optimization

Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

Increased gate length at given footprint for nanosheet device

Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors

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Albany, NY, United States of America

Julien Frougier