Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

Université Joseph Fourier

Julien Buckley

Rene Escoffier

René Escoffier

Haykel Ben Jamaa

Yannick Baines

Matthew Charles

Hubert Bono

Gabriel Molas

Xavier Chevalier

Eric Jalaguier

Thierry Baron

Guy Feuillet

Olivier Billoint

Guillaume Delapierre

Patrick Leduc

Pierre Mur

Erwan Morvan

Jesus Zuniga Perez

Blend Mohamad

Karim Aissou

Guy Royal

Florian Rigaud-Minet

Jérôme Biscarrat

Blandine Alloing

Alphonse Torres

Roy Dagher

A micro-electronic device includes a first electronic component and a second electronic component, and a substrate formed of a first semiconductor material for supporting the components. The first component and the second component each include an active layer formed at least partially from a second semiconductor material different from the first semiconductor material. The device further includes, for each of the components, a stack for maintaining electrical voltage, which stack is situated between the substrate and the active layer of the electronic component under consideration and which comprises two layers forming a junction P-N formed from the same semiconductor material as the substrate and which insulates the relevant active layer from the substrate. The assemblies respectively including the first component and the second component and their respective stack for maintaining electrical voltage are separated from each other by a barrier made of electrically insulating material.

Micro-electronic device with insulated substrate, and associated manufacturing method

A method for obtaining mesas that are made at least in part of a nitride (N), the method includes providing a stack comprising a substrate and at least the following layers disposed in succession from the substrate a first layer, referred to as the flow layer, and a second, crystalline layer, referred to as the crystalline layer; forming pads by etching the crystalline layer and at least one portion of the flow layer such that: —each pad includes at least: —a first section, referred to as the flow section, formed by at least one portion of the flow layer, and a second, crystalline section, referred to as the crystalline section, framed by the crystalline layer and overlying the flow section, the pads are distributed over the substrate so as to form a plurality of sets of pads; and epitaxially growing a crystallite on at least some of said pads and continuing the epitaxial growth of the crystallites until the crystallites carried by the adjacent pads of the same set coalesce.

Method for producing nitride mesas each intended to form an electronic or optoelectronic device

A semiconductor diode, including: a first doped semiconductor region of a first conductivity type; a second doped semiconductor region of a second conductivity type opposite to the first conductivity type, arranged on top of and in contact with the upper surface of the first semiconductor region; a first conductive region arranged on top of and in contact with the upper surface of the second semiconductor region, the first conductive region comprising a through opening opposite a portion of the second semiconductor region; a second conductive region made of a material different from that of the first conductive region, coating the upper surface of the second semiconductor region opposite said opening; a cavity extending through the second conductive region and through the second semiconductor region opposite a portion of said opening; a dielectric region coating the lateral walls and the bottom of the cavity; a third conductive region coating the dielectric region on the lateral walls and at the bottom of the cavity, the third conductive region being further electrically in contact with the first and second conductive regions.

Semiconductor diode and method of manufacturing such a diode

A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.

Transistor association

A field effect transistor includes a substrate; a semiconductor structure formed on a main face of the substrate, the semiconductor structure including a channel area; a first electrode and a second electrode between which extends the channel area, the first electrode including a plurality of portions spaced apart from each other, each portion of the first electrode contributing to forming an elementary transistor referred to as island; connection tracks for electrically connecting the portions of the first electrode to one another; and in which each portion of the first electrode is connected to a connection track through a fuse area, each fuse area associated with the portion of the first electrode of an island being capable of being broken in such a way as to electrically insulate said island if it is defective.

Field effect transistor and associated manufacturing method

Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.

Electron gas transistor, one-piece device comprising at least two transistors in cascode and associated manufacturing methods

A JBS diode includes a substrate; a first semiconductor layer arranged on a first face of the substrate and having a first type of conductivity, the first semiconductor layer including a projecting portion delimited by a trench; a second semiconductor layer arranged on the projecting portion and having a second type of conductivity opposite to the first type of conductivity; an electrically insulating layer arranged at the bottom of the trench; a first electrode including a first portion in Schottky contact with the first semiconductor layer, the first portion being arranged on the electrically insulating layer and against a side wall of the projecting portion of the first semiconductor layer; a second portion in ohmic contact with the second semiconductor layer; a second electrode in ohmic contact with the substrate.

Junction barrier Schottky diode

An integrated electronic device includes a first terminal and a second terminal, a Schottky diode having a first threshold voltage and coupled between the first terminal and the second terminal, a derivation component having a second threshold voltage greater than the first threshold voltage and coupled between the first terminal and the second terminal. The derivation component comprises a super-junction.

Electronic power device with super-junction

A normally-off heterojunction field-effect transistor is provided, including a superposition of a first layer, of III-N type, and of a second layer, of III-N type, so as to form a two-dimensional electron gas; a stack of an n-doped third layer making electrical contact with the second layer, and of a p-doped fourth layer placed in contact with and on the third layer, a first conductive electrode and a second conductive electrode making electrical contact with the two-dimensional electron gas; a dielectric layer disposed against a lateral face of the fourth layer; and a control electrode separated from the lateral face of the fourth layer by the dielectric layer.

Open type heterojunction transistor having a reduced transition resistance

The invention aims for a polarisation circuit of a power component comprising a capacitive dividing bridge and a resistive dividing bridge formed on the same substrate as the component. An additional electrode' in the front faceof the substrate makes it possible to adjust one of the capacitance values of the capacitive dividing bridge according to the other of the capacitance values coming from one of the electrodes of the power component. The sizing of this additional electrode furthermore makes it possible to obtain a leakage resistance contributing to the resistive dividing bridge. Alternatively, two additional resistances R, R&#x2032; formed in the front face of the substrate making it possible to obtain the resistive dividing bridge independently of the capacitive dividing bridge.

Polarization circuit of a power component

An optocoupler is provided, including at least one light source and at least one matrix of photovoltaic cells facing the at least one light source, the at least one light source being configured to receive, at an input, an input electrical signal, and to generate, at an output, according to the input electrical signal, a light signal, sent to the at least one matrix of photovoltaic cells, the at least one matrix of photovoltaic cells being configured to receive, at the input, at least partially the light signal and to deliver, at the output, at least one output electrical signal, at the level of at least two connection pads, and the at least one light source being a matrix of laser diodes.

Optocoupler

A high-electron-mobility field-effect transistor includes a superposition of first and second layers of semiconductor materials so as to form an electron gas layer and includes a gate stack arranged on the superposition. The gate stack includes a conductive electrode and an element made of p-doped semiconductor material, arranged between the conductive electrode and the superposition. The gate stack includes a first dielectric layer arranged between the conductive electrode and the element made of semiconductor material. The element made of semiconductor material, the first dielectric layer, and the conductive electrode have aligned lateral flanks.

High electron mobility transistor and method of fabrication having reduced gate length and leak current

An electronic circuit is provided, including, on one same substrate, an inverter branch formed by high side and low side transistors, and the drivers of the high side and the low side transistors. The drivers include logic gates configured to receive one same PWM input signal and to generate two alternated command signals sent to the high side and the low side transistors. An inverter system is also provided, including the electronic circuit and laser optocouplers configured to electrically insulate the electronic circuit of a controller delivering a pulse width modulation (PWM) input signal and a main supply electrically supplying the drivers.

Inverter branch driver

A heterojunction diode is provided, including first and second semiconductor layers made of III-N material, the layers being superposed to form a two-dimensional electron gas; an anode and a cathode that are selectively electrically connected to each other by the electron gas; a third semiconductor layer positioned under the gas; a p-doped first semiconductor element contacting the anode the third layer, and forming a separation between the anode and the third layer; and an n-doped second semiconductor element contacting the cathode and the third layer, and forming a separation between the cathode and the third layer, the third layer and the first and second elements forming a p-i-n diode.

Heterojunction diode having an increased non-repetitive surge current

The invention relates to a normally-off high-electron-mobility field-effect transistor having a superposition of a first layer of semiconductor material and a second layer of semiconductor material so as form an electron gas layer at the interface between the first and second layers. A trench separates the superposition into first and second domains. An insulating element is positioned in the trench in order to electrically insulate the first and second domains. A p-doped semiconductor element is in contact with the first or the second layer of semiconductor material of the first and second domains, and extends continuously between the first and second domains. A gate insulator is positioned on the semiconductor element and a gate electrode is positioned on the gate insulator.

Growing community of inventors

Grenoble, France

Julien Buckley