Taiwan Semiconductor Manufacturing Comp. Ltd.

Juei-Wen Lin

Yuan-Ko Hwang

Kuei-Jen Chang

Tsung-Chi Hsieh

Jen-Yung Tseng

A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.

Method and apparatus for in-situ descum/hot bake/dry etch photoresist/polyimide layer

A process for creating a fuse structure opening in a stack of materials comprised with overlying dielectric layers, and comprised with an underlying polysilicon layer, to expose a conductive fuse structure, has been developed. The process initiates with a dry etching procedure used to create an initial fuse structure opening in the dielectric layers, using a photoresist shape as an etch mask. Subsequent removal of the photoresist shape results in the completion of the fuse structure opening via in situ etching of the polysilicon layer exposed in the initial fuse structure opening. The isotropic wet etch procedure used for photoresist removal and in situ patterning of polysilicon, avoids polysilicon spacer formation on the sides of the conductive fuse structure, which would have been present with the use of an all dry etch procedure. In addition the wet etch procedure selectively terminates on a thin silicon oxide layer, located on the underlying conductive fuse structure.

Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure

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Tai-Chung, Taiwan

Juei-Wen Lin