Taiwan Semiconductor Manufacturing Comp. Ltd.

Jue-Jye Chen

Yuan-Chang Huang

Yuh-Jier Mii

Shu-Lan Ying

Yeh-Jye Wann

The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.

Test site and a method of monitoring via etch depths for semiconductor

The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.

A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed through a polysilicon gate structure, into the underlying channel region. The ability to reproducibly place the desired dopant at the desired channel location, is dependent on the implant conditions as well as the reproducibility of the thicknesses of the layers the implant has to penetrate. This process has been designed to remove some of the variables and thus result in optimized device characteristics.

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I Lan, Taiwan

Jue-Jye Chen