Applied Materials, Inc.

Novellus Systems Incorporated

Intevac, Inc.

Judy H Huang

David Wingto Cheung

Chi-I Lang

Wai-Fan Yau

Sunil Shanker

Michael S Barnes

Joe Feng

Christopher Dennis Bencher

Sudha S Rathi

Bok Hoen Kim

Raashina Humayun

Kevin P Fairbairn

Gerald Z Yin

Yunsang Kim

Farhad K Moghadam

Christopher S Ngai

Claes H Bjorkman

Mark A Fodor

Kuowei Liu

Vishal Gauri

Dennis J Yost

Betty Tang

Hongquing Shan

Nasreen Gazala Chapra

Sebastien Raoux

Minh Anh Nguyen

William N Taylor

Wenxian Zhu

Chris Ngai

Min Melissa Yu

Karthik Janakiraman

Mei-Yee Shek

Chan-Lon Yang

Dian Sugiarto

Justin F Gaynor

Ping Xu

Mandar Mudholkar

David Silvetti

Madhu Deshpande

Peter W Lee

Terry Bluck

Vinay K Shah

Jengyi Yu

Alexander Berger

Kegang Huang

Henner Meinhold

Ratsamee Limdulpaiboon

Thomas E Deacon

William Nixon Taylor, Jr

Fred J Chetcuti

Kenneth Tan

Chris D Bencher

S&eacute;bastien Raoux

Archita Sengupta

Choon Kun Ryu

Melissa Min Yu

Young Kyu Cho

Greg Stumbo

Sean Cox

Ken Vo

Mei Yee Shek

Joel Glenn

Chau T Nguyen

A plasma processing chamber having capacitive and inductive coupling of RF power. An RF power source is connected to an inductive coil and to a top electrode via a variable capacitor to control the ratio of power applied to the coil and electrode. The bottom electrode, which is part of the chuck holding the substrates, is floating, but has parasitive capacitance coupling to ground. No RF bias is applied to the chuck and/or the substrate, but the substrate is chucked using DC power. In a system utilizing the chamber, the chuck is movable and is loaded with substrates outside the chamber, enter the chamber from one side for processing, exit the chamber from an opposite side after the processing, and is unloaded in an unloading chamber. The chuck is then transported back to the loading chamber. Substrates are delivered to and removed from the system using conveyor belts.

Inductive/capacitive hybrid plasma source and system with such chamber

Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.

Flowable film dielectric gap fill process

Disclosed are methods and apparatus for masking of substrates for deposition, and subsequent lifting of the mask with deposited material. Masking materials are utilized that can be used in high temperatures and vacuum environment. The masking material has minimal outgassing once inside a vacuum chamber and withstand the temperatures during deposition process. The mask is inkjeted over the wafers and, after deposition, removed using agitation, such as ultrasonic agitation, or using laser burn off.

Method and apparatus for masking solar cell substrates for deposition

The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si&#x2014;OH, Si&#x2014;H and Si&#x2014;O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

CVD flowable gap fill

The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.

Semiconductor device having silicon carbide and conductive pathway interface

This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift

The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).

In situ deposition of a low &#x3ba; dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application

High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.

Stress profile modulation in STI gap fill

Plasma etch processes incorporating H/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

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The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. The invention also provides processing regimes that include using an organosilane as a silicon and carbon source, perhaps independently of any other carbon source or hydrogen source, and preferably in the absence of a substantial amount of oxygen to produce a SiC with a dielectric constant of less than 7.0. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).

In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application

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Los Gatos, CA, United States of America

Judy H Huang