United Microelectronics Corp.

Other

United Integrated Circuits Corp.

Juan-Yuan Wu

Water Lur

Chih-Chien Liu

Ming-Sheng Yang

Coming Chen

Hsueh-Chung Chen

Shih-Wei Sun

Peng-Yih Peng

Chien-Hsin Lai

Ta-Shan Tseng

Kun-Lin Wu

Hsueh-Hao Shih

Juen-Kuen Lin

Chih-Chiang Yang

Hao-Kuang Chiu

Daniel Chiu

Wen-Bin Shieh

Cheng-Yuan Tsai

Chao-Yuan Huang

Chien-Hung Chen

Chia-Jui Chang

Tri-Rung Yew

Tony Lin

Kuo-Tai Huang

Kuan-Cheng Su

Wen-Yi Hsieh

Wen-Kuan Yeh

Yimin Huang

Chih-Hsiang Hsiao

Mu-Chun Wang

Gwo-Shii Yang

Jenn Tsao

Chih-Yung Lin

Fu-Tai Liou

Michael W C Huang

Chien-Chao Huang

Tsang-Jung Lin

Kevin Hsieh

Kuen-Jian Chen

Alan Cheng

Wen Bin Shieh

Water Lu

Cheng-Yuan-Chen Tsai

A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

High density plasma chemical vapor deposition process

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Chemical mechanical polishing in forming semiconductor device

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Chemical mechanical polishing for forming a shallow trench isolation structure

A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Method of forming partial reverse active mask

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed A number of shallow trenches are formed between the active regions An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed The oxide layer is planarized to expose the silicon nitride layer.

A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

Method for forming dielectric layers

A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Method of designing active region pattern with shift dummy pattern

A method of photolithography. An anti-reflective coating is formed on the conductive layer. An nitrogen plasma treatment is performed. A photo-resist layer is formed and patterned on the anti-reflective coating. The conductive layer is defined. The photo-resist layer is removed. The anti-reflective layer is removed by using phosphoric acid.

Method of photolithography

A polarization method that utilizes a chemical-mechanical polishing operation. In the polishing operation, slurry for polishing a metallic layer is first employed to remove a greater portion of the metallic layer. Next, slurry for polishing a dielectric layer and having properties very similar to the metal-polishing slurry is added and mixed together with the slurry for polishing a metallic layer so that the polishing rate for the dielectric layer is increased. Consequently, metallic residues remaining on the dielectric layer are removed and a planar dielectric layer is obtained at the same time.

Method of planarization

The present invention provides a monitoring method for monitoring a semiconductor wafer, in a chemical mechanical polishing (CMP) process. The CMP process is used to polish a dielectric layer of the semiconductor. The monitoring method comprises: 1. exposing the dielectric layer of the semiconductor wafer to an input light beam of fixed wavelength at a predetermined angle to generate a reflected light beam within a predetermined time period after performing the CMP process, the intensity of the reflected light beam undergoing periodic changes in response to the gradual thinning of the dielectric layer during the CMP process, 2. monitoring the intensity of the reflected light beam at a starting period within the predetermined time period and obtaining a periodic change rule according to the periodic changes of the intensity of the reflected light beam, and 3. monitoring the intensity of the reflected light beam throughout the rest of the predetermined time period and generating an output signal to stop the CMP process if the change of the intensity of the reflected light beam is not in accordance with the periodic change rule.

Method for monitoring a semiconductor wafer in a chemical mechanical polishing process

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Hsin-Chu, Taiwan

Juan-Yuan Wu