Samsung Electronics Co., Ltd.

Ju-Tae Moon

Young-Min Kim

Seung-Hwan Lee

Seok-Jun Won

Young-Sun Kim

Young-Wook Park

Young-Dae Kim

Kyung-hoon Kim

Sang-Hyeop Lee

Se-Jin Shim

You-Chan Jin

Kab-Jin Nam

Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Integrated circuit capacitors having doped HSG electrodes

Methods of forming integrated circuit capacitors having doped HSG electrodes

Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby

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Ju-Tae Moon