Skhynix Inc.

Ju Il Eom

Jae Hoon Lee

Byung Jun Bang

Han Jun Bae

Seung Yeop Lee

Won Duck Jung

Sang Joon Lim

Sung Ho Hyun

Hyung Ho Cho

Jin Kyoung Park

Woo Jin Lee

Bok Kyu Choi

Jong Wook Kim

Jin Hwan Song

A substrate in accordance with an embodiment of the disclosure includes a signal transmission layer including a signal transmission pad and a signal transmission interconnection; a first dielectric layer stacked on the signal transmission layer; and a first reference voltage layer stacked on the first dielectric layer. The first reference voltage layer includes a first space hole and an impedance calibrator. The impedance calibrator includes an impedance calibration part disposed in the first space hole; and a first bridge connecting a first portion of the impedance calibration part to a first portion of the first reference voltage layer.

Substrate including a reference voltage layer having an impedance calibrator

A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.

Semiconductor chip including chip pads of different surface areas, and semiconductor package including the semiconductor chip

A semiconductor package includes a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.

Semiconductor package and semiconductor module including the same

A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface that is connected to the signal redistribution pad and a lower surface that is connected to the substrate; a power sub interconnector with an upper surface that is connected to the power redistribution pad and a lower surface that is connected to the substrate; and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate.

Semiconductor package including stacked semiconductor chips

A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.

Semiconductor chip having chip pads of different surface areas, and semiconductor package including the same

A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

Semiconductor package including an interposer

A semiconductor package includes: a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.

A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.

A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.

A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

Semiconductor package including capacitor

A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion on a substrate body. First to third via landing portions are spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed side by side. A first guard trace portion is substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion. The first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion. A semiconductor chip mounted on the package substrate includes first inner chip pads and first outer chip pads bonded to the package substrate.

Semiconductor packages

A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

Semiconductor package having a redistribution line structure

According to one embodiment, a semiconductor package includes a band stop filter, which includes: a transmission line pattern arranged on a package substrate; and a conductive stub pattern arranged along the transmission line pattern in a state of being separated from the transmission line pattern.

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Guri-si, South Korea

Ju Il Eom