Taiwan Semiconductor Manufacturing Comp. Ltd.

Jr-Jung Lin

Chih-Han Lin

Che-Cheng Chang

Chang-Yin Chen

Chao-Cheng Chen

Ming-Ching Chang

Yung Jung Chang

Tung-Wen Cheng

Yung-Jung Chang

Shih-Yao Lin

Chun-Hung Lee

Mu-Tsang Lin

Jin-Aun Ng

Shih-Hao Chen

Ryan Chia-Jen Chen

Chun-Lung Ni

Chi-Wei Yang

Yun-Ting Chou

Chien-Hao Chen

Yih-Ann Lin

Po-Chi Wu

Yi-Jen Chen

Chih Hsuan Wang

Chen-Yu Wu

Chih Ping Wang

Pei-Hsiu Wu

Yun Ting Chou

Yung-Cheng Lu

Ming-Hsi Yeh

Huan-Just Lin

Kuo-Tai Huang

Yi-Shien Mor

Chi-Kang Liu

Yi-Hsing Chen

Yi-Cheng Li

Buh-Kuan Fang

Sung-Hsun Wu

Ricky Wang

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Gate structure with non-linear profile for transistors

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Mechanisms for forming FinFET device

An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Dummy fin between first and second semiconductor fins

A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

Method and structure for FinFET isolation

A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Dummy fin profile control to enlarge gate process window

Method of forming a dummy fin between first and second semiconductor fins

A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features

Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

Metal gate electrode of a semiconductor device

Gate structure with desired profile for semiconductor devices

Dummy FIN profile control to enlarge gate process window

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Gate structure of field effect transistor with footing

Semiconductor device having dummy fin physically separating the first and second gate stacks

An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.

FinFET structures and methods of forming the same

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Hsinchu, Taiwan

Jr-Jung Lin