Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Jozef C Mitros

Xiaoju Wu

Imran Khan

Victor Ivanov

Taylor R Efland

Pinghai Hao

Chin-Yu Tsai

Louis N Hutter

Lily Springer

Ralph Oberhuber

William E Nehrer

Binghua Hu

Weidong Tian

Alec James Morton

Sameer P Pendharkar

James Robert Todd

Keith Edmund Kunz

John P Erdeljac

Dan M Mosher

Jeffrey P Smith

Dirk Preikszat

Roland Bucksch

Keith M Jarreau

David A Heisley

David A Tatman

James (Bob) Todd

Lou Hutter

Sam Shichijo

A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Reduced area single poly EEPROM

Electrically erasable programmable 'read-only' memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Area-efficient electrically erasable programmable memory cell

A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the source-to-floating gate capacitance is substantially greater than the drain-to-floating gate capacitance. The source-to-floating gate capacitance is, for example, at least about three times greater than the drain-to-floating gate capacitance to enable the memory device to be electrically programmed or erased by applying a potential between a source electrode and a drain electrode without using a control gate. A current path between the source and drain electrodes generally defines current carrying portions of the source and drain regions, and a non-current carrying portion of the source region residing outside the current carrying portion, wherein substantially more of the floating gate overlies the non-current carrying portion than the current carrying portions.

Single poly EEPROM without separate control gate nor erase regions

A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read transistor isolated within a well of the first conductivity type, and a floating gate overlying a portion of the control gate, the read transistor, and the first and second tunneling regions. The memory device is configured to be electrically programmed by changing a charge on the floating gate that changes the device threshold voltage. In one embodiment, the memory device is configured to be electrically programmed by applying a first potential between the first and second tunneling regions, and a second potential to the control gate, the second potential having a value less than the first potential.

Analog single-poly EEPROM incorporating two tunneling regions for programming the memory device

A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.

Method to detect poly residues in LOCOS process

Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.

Methods for reducing capacitor dielectric absorption and voltage coefficient

An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

Embedded EEPROM array techniques for higher density

The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Memory device with reduced cell area

Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.

Methods of performance improvement of HVMOS devices

A method forming a current path in a substrate () having a first conductivity type is disclosed. The method includes forming an impurity region () having a second conductivity type and extending from a face of the substrate to a first depth. A hole () is formed in the impurity region. A first dielectric layer (-) is formed on an inner surface of the hole. A first electrode () is formed in the hole adjacent the dielectric layer.

EEPROM with etched tunneling window

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Semiconductor device with an analog capacitor

A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor () having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM () will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region () within a semiconductor substrate (), and forming a drain region () of the OTP EPROM () within the p-doped region ().

One time programmable EPROM for advanced CMOS technology

The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vimplant into a channel region of an n-well that substantially underlies a floating gate structure. The Vimplant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vimplant.

Growing community of inventors

Richardson, TX, United States of America

Jozef C Mitros