Taiwan Semiconductor Manufacturing Comp. Ltd.

Alpha & Omega Semiconductor Corporation

Siliconix Incorporated

Integrated Device Technology, Inc.

Jowei Dun

Ying-Lang Wang

Fwu-Iuan Hshieh

Yueh-Se Ho

Wenjun Li

Hongyong Xue

Mike F Chang

King Owyang

Sik Lui

Hong Chang

Yeeheng Lee

Paul Thorup

Yiming Gu

Hung-Ju Chien

Chun-Ching Tsan

Hui-Ling Wang

Terence Huang

Yang Xiang

Ken-Shen Chou

Ching-Kai Lin

Yi Chang Yang

Chuen-Der Lien

Szu-An Wu

Yu-Ku Lin

Reinhard Zachai

Jun Wu

Tong-Hua Kuan

Bosco Lan

Hway-Chi Lin

Jiun-Chung Lee

Daniel J Liao

Ming-Jer Lee

Hans-Jurgen Fusser

Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Self-aligned contact for trench power MOSFET

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Power device with high aspect ratio trench contacts and submicron pitches between trenches

A semiconductor wafer having a double inter-metal dielectric layer formed in the gaps of and on closely. spaced metal interconnection circuitry. The double dielectric layer is formed by an in situ low temperature two step deposition HDP-CVD process separated by a cool-down period. The low temperature process mitigates metal line defects such as distortion or warping caused by heat generated during the process of filling gaps having aspect ratios greater than 2. The double dielectric layer is composed of Group IV materials, silicon being the preferred material. These double layers may be individually doped. Titanium nitride layers, present as by-products of seeding and anti-reflective coatings serve to reduce electro-migration of the metal circuitry.

Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry

A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.

Reduction of tungsten damascene residue

A new method is provided for the creation of layers of dielectric that are used for metal stack interconnect layers where the metal stack exceeds five layers. A stack of five layers of metal interconnect lines contains one layer of Intra Metal dielectric (ILD) and four layers of Inter Metal dielectric (IMD). One or more of the layers of IMD can be formed in the conventional method. One or more of the layers of IMD can be formed in the conventional method after which a layer of high compressive PECVD is deposited over this one or more layers of IMD. The layer of high compressive PECVD provides a crack resistant film that eliminates the formation of cracks in the surface of the IMD.

Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue

Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

Three-dimensional type inductor for mixed mode radio frequency device

A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity

This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.

Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry

An improved method for removing residual slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing has been developed. The cleaning method involves sequential spray cleaning solutions of NH.sub.4 OH and H.sub.2 O, NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, HF and H.sub.2 O, and HCl, H.sub.2 O.sub.2 and H.sub.2 O. The cleaning sequence is: 1. A pre-soak in a spray solution of NH.sub.4 OH and H.sub.2 O; 2. Spray cleaning in a solution of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O; 3. Spray cleaning in a dilute solution of HF and H.sub.2 O; 4. Spray rinsing in DI-water. It is important that slurry particulates first be removed by NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, followed by spray cleaning in a dilute solution of HF and H.sub.2 O to remove metallic residues. The spray cleaning method is superior to brush cleaning methods for both oxide-CMP and tungsten-CMP and results in superior removal of slurry particles and metallic residues introduced by the CMP processes. An optional spray cleaning step using a solution of HCl, H.sub.2 O.sub.2 and H.sub.2 O results in further reduction of metallic residue contamination following oxide-CMP. Compared to traditional brush cleaning the new spray cleaning process has a 2.times. improvement in throughput, less consumption of DI water, and low risk of cross-contamination between sequentially cleaned substrates.

Process for cleaning a semiconductor substrate after chemical-mechanical

A method is described for improving the step coverage of tungsten interconnects and plugs when deposited at low temperatures into contact/via openings having high aspect ratios. The depositions are made at pressures between 4.5 and 100 Torr in a CVD tool. The method includes a first nucleation step, and a second step for filling the contact/via openings wherein deposition conditions favor good step coverage. For forming an interconnect and a third deposition step, providing moderate step coverage and low stress, is used to build up the interconnect. The high pressures permit deposition at practical rates at low temperatures. In addition the high pressures also permit application of backside gas pressure to the wafer during deposition, thereby improving the thermal contact between the wafer and the heated substrate holder. This contributes significantly to stress reduction and improved step coverage.

Method for reducing stress and improving step-coverage of tungsten

A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.

Fabrication of high-density trench DMOS using sidewall spacers

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

Surface mount and flip chip technology with diamond film passivation for

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

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San Jose, CA, United States of America

Jowei Dun