Taiwan Semiconductor Manufacturing Comp. Ltd.

Joung-Wei Liou

Keng-Chu Lin

Chin Kun Lan

Hui-Chun Yang

Yu-Yun Peng

Po-Cheng Shih

Yi-Wei Chiu

Chia Cheng Chou

Shwang-Ming Jeng

Mei-Ling Chen

Chih-Hung Sun

Bo-Jhih Shen

Chung-Chi Ko

Kuang-Yuan Hsu

Cheng-Han Wu

Ya Hui Chang

Chia-Cheng Chou

Han-Ti Hsiaw

Han-Ting Tsai

Li-Te Hsu

Cheng-Yi Wu

Shih-Ho Lin

Shih-Wen Huang

Chin-Hsing Lin

Chia-I Shen

Jinn-Kwei Liang

Fei-Fan Chen

Chien Kuo Huang

Kuang-I Liu

Szu-An Wu

Yu Lun Ke

Tze-Liang Lee

Chih-Ming Ke

Chia-Hui Lin

Ming-Te Chen

Chien-Feng Lin

Jacky Huang

Ying-Hsiu Tsai

Yi-Jung Liu

Tsang-Yu Liu

Cheng-Liang Chang

Huan-Wei Wu

Chester Tang

Shiauhan Wu

Yin-Ping Lee

Greg Huang

A method of wafer processing includes supporting a wafer in a process chamber. The method further includes introducing a flow of a gaseous material through an inlet of the process chamber to process the wafer. The method further includes generating, between the inlet and the wafer, controllable forces acting in various directions on the gaseous material to spread the gaseous material inside the process chamber.

Wafer processing method

The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.

Interlayer dielectric layer

The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Semiconductor structure having high breakdown voltage etch-stop layer

An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Spacer scheme and method for MRAM

A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Photoresist and method of formation and use

The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Spacer stack for magnetic tunnel junctions

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Magnetic tunnel junction device and method of forming same

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

Hardened interlayer dielectric layer

Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and Ogas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where Ogas may be used and, along with the Ogas, precursors containing embedded Si—O—Si bonds, such as (CHO)—Si—O—Si—(CHO)) and (CH)—Si—O—Si—(CH)may be used.

Interconnect system with improved low-K dielectrics

An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

An exemplary method that forms spacer stacks with metallic compound layers is disclosed. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer&#x2014;which includes a metallic compound&#x2014;over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Methods for forming a spacer stack for magnetic tunnel junctions

High breakdown voltage inter-metal dielectric layer

Growing community of inventors

Zhudong Town, Taiwan

Joung-Wei Liou