International Business Machines Corporation

Elpis Technologies Inc.

Joshua M Rubin

Tenko Yamashita

Alexander Reznicek

Terence B Hook

Chen Zhang

Bruce Bennett Doris

Lawrence Alfred Clevenger

Arvind Kumar

Junli Wang

Shogo Mochizuki

Steven Lorenz Wright

Kamal Kumar Sikka

Heng Wu

Charles Leon Arvin

Praneet Adusumilli

Oscar Van Der Straten

Brent A Anderson

Balasubramanian Pranatharthiharan

Pranita Kerber

Dinesh Gupta

Ardasheir Rahman

Ravi K Bonam

Maryse Cournoyer

Terry Hook

Kangguo Cheng

Ali Khakifirooz

Pouya Hashemi

Nicolas J Loubet

Son Van Nguyen

Hong He

Todd Edward Takken

Jon Alfred Casey

Mark William Kapfhammer

Steve Ostrander

Valérie Anne Oberson

Robin M Schulz

Ruilong Xie

Veeraraghavan S Basker

Xin Miao

William John Starke

John Ulrich Knickerbocker

Oleg Gluschenkov

Ramachandra Divakaruni

Hemanth Jagannathan

Mukta G Farooq

Timothy Joseph Chainer

Fee Li Lie

Bing Dang

Paul Stephen Andry

Sami Rosenblatt

Joel Abraham Silberman

Xiao Hu Liu

Markus Brink

Indira P Seshadri

Robert Allen Groves

James John Kelly

Wiren Dale Becker

Vivekananda P Adiga

Qianwen Chen

Jared Barney Hertzberg

Shurong Tian

Mounir Meghelli

Yang Liu

Iqbal Rashid Saraf

Dale Curtis McHerron

Adiga Vivekananda

A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

Dummy fin contact in vertically stacked transistors

An exemplary apparatus includes a substrate; a plurality of chips mounted onto the substrate; a plurality of cold plates corresponding to the plurality of chips; means for pressing each of the cold plates toward a corresponding one of the chips; means for delivering coolant flow to the cold plates; and means for adjusting the cooling power of the plurality of cold plates, responsive to at least one sensed parameter of the plurality of chips.

Heterogeneous integrated multi-chip cooler module

An apparatus includes a cabinet; an air-mover attached to the cabinet; a circuit board mounted in the cabinet; and an air-cooled heat sink attached in thermal contact with a heat-generating component on the circuit board. The heat sink includes a heat sink base; primary heat removal fins protruding from the heat sink base in a direction away from the circuit board; and secondary heat removal fins protruding from the heat sink base in a direction toward the circuit board. The air-mover is configured to force air between the primary heat removal fins and between the secondary heat removal fins.

Heat sinks with beyond-board fins

A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

Back-side memory element with local memory select transistor

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Interconnection structures for high bandwidth data transfer

An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Vertical FET with contact to gate above active fin

A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Reducing gate resistance in stacked vertical transport field effect transistors

One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including 'die first' and 'die last' methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

Precision thin electronics handling integration

A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

Transferrable pillar structure for fanout package or interconnect bridge

A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.

Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

A method comprising forming at least one fin on a substrate, wherein the at least one fin has a first section and a second section. Forming a separating layer on the substrate to isolate the second section of the fin from the first section of the fin. Forming as first set of electrical components on the first section of the at least one fin. Flipping the substrate over and removing the substrate to expose a surface of the second section of the at least one fin. Removing a portion of the second section of the at least one fin, whereby removing a portion of the second section a trench is created between sections of the separating layer and an exposed portion of the at least one fin and forming a hard mask in the trench.

Fin top hard mask formation after wafer flipping process

A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.

Gate metal patterning to avoid gate stack attack due to excessive wet etching

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Direct bonded heterogeneous integration packaging structures

A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.

Contact formation for stacked vertical transport field-effect transistors

Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Multi-chip package structures with discrete redistribution layers

Growing community of inventors

Albany, NY, United States of America

Joshua M Rubin