Motorola Corporation

Freescale Semiconductor,inc.

Joseph Petrucci

Karl Emerson Mautz

John George Maltabes

Alain Bernhard Charles

A lithography and etching method for forming an alignment mark () and at least one device feature (such as a shallow trench) on a wafer () is provided. The etching process () comprises: a first etching step () for pre-defining at least one alignment mark () and a second etching step () for defining desired semiconductor device patterns (such as a shallow trench) on said wafer surface and completing said at least one alignment mark ().

Method for defining alignment marks in a semiconductor wafer

A semiconductor method for reducing charge damage during plasma etch processing is disclosed. Structures ( ) for accumulating charge during plasma etch processing are provided on a semiconductor wafer ( ), the structures ( ) being electrically connected to device structures ( ).

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New Milford, CT, United States of America

Joseph Petrucci