United States of America as Represented by the Secretary of the Air Force

USA as Represented by Secretary of the Navy

Joseph P Lorenzo

Richard A Soref

Kenneth Vaccaro

Eric A Martin

Andrew Richard Davis

Helen M Dauplaise

William A Waters

Stephen M Spaziani

Andrew C Yang

Brian R Bennett

An aqueous thiourea-ammonia treatment is used to form a thin sulfurous film at the indium phosphide surface, having a thickness of less than one nanometer. The thiourea-ammonium hydroxide treatment can be used as is or immediately prior to deposition of cadmium sulfide for enhanced surface passivation. The thiourea-ammonium hydroxide treatment is entirely compatible with chemical bath deposition, molecular beam epitaxy, or metalorganic chemical vapor deposition of the cadmium sulfide.

Method for obtaining a sulfur-passivated semiconductor surface

A novel indium phosphide (InP) based heterojunction bipolar transistor (HBT) is described. A II-VI compound, cadmium sulfide (CdS), is used as the emitter to improve the emitter injection efficiency and reduce recombination losses. The cadmium sulfide emitter is applied following the epitaxial growth of III-V compound collector and base regions. The large valence band discontinuity (.quadrature.E=0.75 eV) between CdS and InP allows InP to be used for both the base and collector material. Prior to cadmium sulfide deposition, the exposed surfaces of the epitaxial layers can be passivated with sulfur, further reducing the recombination losses.

Cadmium sulfide layers for indium phosphide-based heterojunction bipolar

In a Schottky metal junction semiconductor device, a CdS interface layer, having a thickness of under 100 angstroms, is positioned under the Schottky barrier gate of a III-V HEMT, for reducing gate leakage, and for enabling full depletion of the conducting channel. A similar layer is positioned under the insulator of an MIS device having an InP substrate. The CdS layers are deposited from a chemical bath which merely entails a simple, safe and readily controllable additional step in the otherwise conventional manufacturing process of these devices.

Cadmium sulfide interface layers for improving III-V semiconductor

A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.

FET optical receiver using backside illumination, indium materials

A full wafer to full wafer integrated circuit apparatus wherein substrate removal and replacement on one wafer has been used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo feed effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Wafer joined optoelectronic integrated circuits

An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.

Backside illuminated MSM device

Backside illuminated MSM device method

A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Wafer joined optoelectronic integrated circuits and method

The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1.3, 1.6 .mu.m or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.

Method of making a lattice mismatched heterostructure optical waveguide

Lattice mismatched hetrostructure optical waveguide

The invention comprises a pyrolytic process for the deposition of high quality silicon dioxide at temperatures of 100.degree.-330.degree. C. Deposition is achieved by reacting silane and oxygen in the 2-12 torr pressure range, yielding deposition rates of 140 .ANG./min at 300.degree. C. and 50 .ANG./min at 120.degree. C. Measurements of refractive index (1.45-1.46), field strength (3-10.times.10.sup.6 V/cm), and resistivity (10.sup.13 -10.sup.15 -cm) indicate that the oxides are near stoichiometric SiO.sub.2. This technology appears promising the Group IV and Group III-V device applications.

Method for the deposition of high quality silicon dioxide at low

The invention comprises integral all silicon light sources and 3-D optical waveguides which combine the functions of room temperature optical emission and optical signal routing. Several light emitting electrooptical silicon devices are herein disclosed. Light emitted by silicon LEDs is concentrated in channels (waveguides) and is directed to desired locations on a silicon wafer. In all of the devices, the light source is electrically actuated by a forward biased p-n junction and the light intensity can be electrically controlled by varying the applied current.

Silicon light-emitting diode with integral optical waveguide

This invention describes an infrared lightwave modulation and switching aratus for very rapidly changing the refractive index of a light-transmitting, doped, semiconductor waveguide. Electrical control is exerted by a MIS diode or MISFET. The apparatus includes a transparent crystalline silicon waveguide, an electrically insulating dielectric layer overlaying a portion of that waveguide, and an elongated, conductive gate electrode in contact with the insulator. A gate voltage applied between the semiconductor and gate serves to deplete free charge carriers from the region of the waveguide under the gate. Elongated source and drain electrodes may be added to enhance electro-optic control.

Metal-insulator-semiconductor control of guided optical waves in

The invention comprises a Schottky barrier type infrared photodetector which is monolithically integrated on a silicon waveguide. A Schottky barrier contact is positioned directly on a silicon waveguide to absorb grazing incidence optical signals passing through the waveguide. The Schottky contact is operated in the avalanche or reverse bias mode to generate a useable electrical signal.

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Stow, MA, United States of America

Joseph P Lorenzo