Cadence Design Systems, Inc.

Joseph P Jarosz

Thaddeus Clay McCracken

Miles P McGowan

Jeffrey Kim Ng

Disclosed are methods, systems, and articles of manufactures for providing evolving information in generating a physical design with custom conductivity using force models and design space decomposition by first presenting a layout area in an interface. The interface then displays the evolution of the physical design in the interface to reflect temporal states of the physical design during generation of the physical design after the system receives an input for the physical design and a request for creating the physical design.

Methods, systems, and articles of manufacture for providing evolving information in generating a physical design with custom connectivity using force models and design space decomposition

Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.

Method and system for implementing an interface for I/O rings

Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete conductivity for the electronic design. The initially identified custom conductivity information is maintained throughout this iterative process.

Methods, systems, and articles of manufacture for implementing physical designs with force directed placement or floorplanning and layout decomposition

An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the user's manipulation of the object until a legal configuration is achieved. The improved approach provides a visual representation that corresponds to the expected end result, but is also be useful to track the user's actions if there is a violation.

Method and system for implementing a user interface with ghosting

Disclosed are improved methods, systems, and computer program products for visualizing and estimating IC die arrangement for an electronic design, and for performing chip planning and estimation based upon the estimated and visualized IC die arrangements. According to some approaches, an interface is provided for visualizing different die arrangement options for an electronic design, in which a filmstrip view is provided to display smaller images of different die arrangement options, and a central viewing area is provided to view a larger image of a selected candidate die arrangement. The different images, whether smaller or larger images, are maintained with design object information and not just static images. This allows for selection and highlighting of individual objects within the die arrangement images, as well as corresponding highlighting of that same object in other images.

Method and system for implementing die size adjustment and visualization

An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.

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Sunnyvale, CA, United States of America

Joseph P Jarosz