International Business Machines Corporation

Other

Joseph Maryan Milewski

Charles Gerard Woychik

Terry Cain Coughlin, Jr

Robert K Montoye

Lawrence Shungwei Mok

Raymond R Horton

Alphonso Philip Lanzetta

Loc Khac Nguyen

Hussain Shaukatulla

Douglas Willard Stout

William Frederick Lawson

Frank E Andros

Christopher G Angulas

James Patrick Libous

Akio Miyoshi

Thomas Subulak

A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.

Low temperature solder chip attach structure and process to produce a high temperature interconnection

Low temperature solder chip attach structure

A chip package comprises a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers. Other embodiments of the composite capacitor/stiffener are also disclosed.

Composite capacitor and stiffener for chip carrier

Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.

5V-tolerant receiver for low voltage CMOS technologies

A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage supply source.

High voltage tolerant receivers

Process to produce a high temperature interconnection

An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.

Electronic package with interconnected chips

Method of fabricating an electronic package with interconnected chips

A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.

Level shifting CMOS I/O buffer

An electronic package and method of making same wherein a flexible circuitized substrate is used to interconnect contact sites on a semiconductor device (chip) to respective conductors on a circuitized substrate (PCB). Significantly, the flexible substrate is coupled to the PCB using solder elements which are applied to the flexible substrate prior to semiconductor device coupling to others of the flexible substrates' conductive elements. These other conductive elements are then connected to the devices' contact sites using thermocompression bonding, the bonding occurring through an aperture in the flexible substrate.

Electronic package structure and method of making same

A smoke alarm having means for detecting smoke and producing a signal in response to the detected smoke is provided with a manually-actuated control which cooperates with the signal producing means to temporarily deactivate the same and to automatically reactivate the same after a predetermined time delay. A temperature responsive override switch is provided to actuate the signal in the event of a fire during the time delay. Thus, a homeowner is able to temporarily deactivate the smoke alarm, such as duringcooking, parties, showering, etc. to thereby prevent the alarm from going off in response to non-fire conditions.

Growing community of inventors

Endicott, NY, United States of America

Joseph Maryan Milewski