Micron Technology Incorporated

Joseph M McCrate

Robert J Gleixner

Nevil N Gajera

Marco Sforzin

Kirthi Shenoy

Brian M Twait

Mohammed Ebrahim Hargan

Paolo Amato

Karthik Sarpatwari

Ramin Ghodsi

Hari Giduturi

Mingdong Cui

Jessica Chen

Josephine Tiu Hamada

Lingming Yang

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

Interleaved Reed-Solomon (IRS) with collaborative decoding

Provided is an apparatus comprising a search engine that (i) receives parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produces corresponding sets of polynomial roots therefrom and a sequence detector that identifies sequences within each of the polynomial roots within the set of roots. The apparatus also includes a sequence check logic that (i) combines the identified sequences within each of the polynomial roots and (ii) performs a sequence check of the combined identified sequences to determine whether only one of the identified sequences is valid; and an error location generator that derives an error location in each of the ECC words within the set responsive to the valid sequence.

Decoder for burst correction read Solomon decoding for memory applications

Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative

Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.

Burst correction reed solomon decoding for memory applications

Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

Iterative decoding technique for correcting DRAM device failures

Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.

Data correction scheme with reduced device overhead

Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

Iterative decoder for correcting dram device failures

A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.

Data protection and recovery

The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages

The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.

Error detection and correction in memory

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

Memory electrodes and formation thereof

Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

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Boise, ID, United States of America

Joseph M McCrate